drivers/net/ethernet/cavium/thunder/nicvf_main.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/cavium/thunder/nicvf_main.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/cavium/thunder/nicvf_main.c- Extension
.c- Size
- 60508 bytes
- Lines
- 2331
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/interrupt.hlinux/pci.hlinux/netdevice.hlinux/if_vlan.hlinux/etherdevice.hlinux/ethtool.hlinux/log2.hlinux/prefetch.hlinux/irq.hlinux/iommu.hlinux/bpf.hlinux/bpf_trace.hlinux/filter.hlinux/net_tstamp.hlinux/workqueue.hnic_reg.hnic.hnicvf_queues.hthunder_bgx.h../common/cavium_ptp.h
Detected Declarations
function nicvf_netdev_qidxfunction nicvf_reg_writefunction nicvf_reg_readfunction nicvf_queue_reg_writefunction nicvf_queue_reg_readfunction nicvf_write_to_mbxfunction nicvf_send_msg_to_pffunction nicvf_check_pf_readyfunction nicvf_send_cfg_donefunction nicvf_read_bgx_statsfunction nicvf_handle_mbx_intrfunction nicvf_hw_set_mac_addrfunction nicvf_config_cpifunction nicvf_get_rss_sizefunction nicvf_config_rssfunction nicvf_set_rss_keyfunction nicvf_rss_initfunction nicvf_request_sqsfunction nicvf_send_vf_structfunction nicvf_get_primary_vf_structfunction nicvf_set_real_num_queuesfunction nicvf_init_resourcesfunction nicvf_xdp_rxfunction nicvf_snd_ptp_handlerfunction nicvf_snd_pkt_handlerfunction nicvf_set_rxhashfunction nicvf_set_rxtstampfunction nicvf_rcv_pkt_handlerfunction nicvf_cq_intr_handlerfunction nicvf_pollfunction nicvf_handle_qs_errfunction nicvf_dump_intr_statusfunction nicvf_misc_intr_handlerfunction nicvf_intr_handlerfunction nicvf_rbdr_intr_handlerfunction nicvf_qs_err_intr_handlerfunction nicvf_set_irq_affinityfunction nicvf_register_interruptsfunction nicvf_unregister_interruptsfunction nicvf_register_misc_interruptfunction nicvf_xmitfunction nicvf_free_cq_pollfunction nicvf_stopfunction nicvf_config_hw_rx_tstampfunction nicvf_update_hw_max_frsfunction nicvf_link_status_check_taskfunction nicvf_openfunction nicvf_change_mtu
Annotated Snippet
static const struct net_device_ops nicvf_netdev_ops = {
.ndo_open = nicvf_open,
.ndo_stop = nicvf_stop,
.ndo_start_xmit = nicvf_xmit,
.ndo_change_mtu = nicvf_change_mtu,
.ndo_set_mac_address = nicvf_set_mac_address,
.ndo_get_stats64 = nicvf_get_stats64,
.ndo_tx_timeout = nicvf_tx_timeout,
.ndo_fix_features = nicvf_fix_features,
.ndo_set_features = nicvf_set_features,
.ndo_bpf = nicvf_xdp,
.ndo_set_rx_mode = nicvf_set_rx_mode,
.ndo_hwtstamp_get = nicvf_hwtstamp_get,
.ndo_hwtstamp_set = nicvf_hwtstamp_set,
};
static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct device *dev = &pdev->dev;
struct net_device *netdev;
struct nicvf *nic;
int err, qcount;
u16 sdevid;
struct cavium_ptp *ptp_clock;
ptp_clock = cavium_ptp_get();
if (IS_ERR(ptp_clock)) {
if (PTR_ERR(ptp_clock) == -ENODEV)
/* In virtualized environment we proceed without ptp */
ptp_clock = NULL;
else
return PTR_ERR(ptp_clock);
}
err = pci_enable_device(pdev);
if (err) {
err = dev_err_probe(dev, err, "Failed to enable PCI device\n");
goto err_put_ptp;
}
err = pci_request_regions(pdev, DRV_NAME);
if (err) {
dev_err(dev, "PCI request regions failed 0x%x\n", err);
goto err_disable_device;
}
err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
if (err) {
dev_err(dev, "Unable to get usable DMA configuration\n");
goto err_release_regions;
}
qcount = netif_get_num_default_rss_queues();
/* Restrict multiqset support only for host bound VFs */
if (pdev->is_virtfn) {
/* Set max number of queues per VF */
qcount = min_t(int, num_online_cpus(),
(MAX_SQS_PER_VF + 1) * MAX_CMP_QUEUES_PER_QS);
}
netdev = alloc_etherdev_mqs(sizeof(struct nicvf), qcount, qcount);
if (!netdev) {
err = -ENOMEM;
goto err_release_regions;
}
pci_set_drvdata(pdev, netdev);
SET_NETDEV_DEV(netdev, &pdev->dev);
nic = netdev_priv(netdev);
nic->netdev = netdev;
nic->pdev = pdev;
nic->pnicvf = nic;
nic->max_queues = qcount;
/* If no of CPUs are too low, there won't be any queues left
* for XDP_TX, hence double it.
*/
if (!nic->t88)
nic->max_queues *= 2;
nic->ptp_clock = ptp_clock;
/* Initialize mutex that serializes usage of VF's mailbox */
mutex_init(&nic->rx_mode_mtx);
/* MAP VF's configuration registers */
nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
if (!nic->reg_base) {
dev_err(dev, "Cannot map config register space, aborting\n");
Annotation
- Immediate include surface: `linux/module.h`, `linux/interrupt.h`, `linux/pci.h`, `linux/netdevice.h`, `linux/if_vlan.h`, `linux/etherdevice.h`, `linux/ethtool.h`, `linux/log2.h`.
- Detected declarations: `function nicvf_netdev_qidx`, `function nicvf_reg_write`, `function nicvf_reg_read`, `function nicvf_queue_reg_write`, `function nicvf_queue_reg_read`, `function nicvf_write_to_mbx`, `function nicvf_send_msg_to_pf`, `function nicvf_check_pf_ready`, `function nicvf_send_cfg_done`, `function nicvf_read_bgx_stats`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.