drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/chelsio/cxgb/fpga_defs.h
Extension
.h
Size
8083 bytes
Lines
234
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __CHELSIO_FPGA_DEFS_H__
#define __CHELSIO_FPGA_DEFS_H__

#define FPGA_PCIX_ADDR_VERSION               0xA08
#define FPGA_PCIX_ADDR_STAT                  0xA0C

/* FPGA master interrupt Cause/Enable bits */
#define FPGA_PCIX_INTERRUPT_SGE_ERROR        0x1
#define FPGA_PCIX_INTERRUPT_SGE_DATA         0x2
#define FPGA_PCIX_INTERRUPT_TP               0x4
#define FPGA_PCIX_INTERRUPT_MC3              0x8
#define FPGA_PCIX_INTERRUPT_GMAC             0x10
#define FPGA_PCIX_INTERRUPT_PCIX             0x20

/* TP interrupt register addresses */
#define FPGA_TP_ADDR_INTERRUPT_ENABLE        0xA10
#define FPGA_TP_ADDR_INTERRUPT_CAUSE         0xA14
#define FPGA_TP_ADDR_VERSION                 0xA18

/* TP interrupt Cause/Enable bits */
#define FPGA_TP_INTERRUPT_MC4                0x1
#define FPGA_TP_INTERRUPT_MC5                0x2

/*
 * PM interrupt register addresses
 */
#define FPGA_MC3_REG_INTRENABLE              0xA20
#define FPGA_MC3_REG_INTRCAUSE               0xA24
#define FPGA_MC3_REG_VERSION                 0xA28

/*
 * GMAC interrupt register addresses
 */
#define FPGA_GMAC_ADDR_INTERRUPT_ENABLE      0xA30
#define FPGA_GMAC_ADDR_INTERRUPT_CAUSE       0xA34
#define FPGA_GMAC_ADDR_VERSION               0xA38

/* GMAC Cause/Enable bits */
#define FPGA_GMAC_INTERRUPT_PORT0            0x1
#define FPGA_GMAC_INTERRUPT_PORT1            0x2
#define FPGA_GMAC_INTERRUPT_PORT2            0x4
#define FPGA_GMAC_INTERRUPT_PORT3            0x8

/* MI0 registers */
#define A_MI0_CLK 0xb00

#define S_MI0_CLK_DIV    0
#define M_MI0_CLK_DIV    0xff
#define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV)
#define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV)

#define S_MI0_CLK_CNT    8
#define M_MI0_CLK_CNT    0xff
#define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT)
#define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT)

#define A_MI0_CSR 0xb04

#define S_MI0_CSR_POLL    0
#define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL)
#define F_MI0_CSR_POLL    V_MI0_CSR_POLL(1U)

#define S_MI0_PREAMBLE    1
#define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE)
#define F_MI0_PREAMBLE    V_MI0_PREAMBLE(1U)

#define S_MI0_INTR_ENABLE    2
#define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE)
#define F_MI0_INTR_ENABLE    V_MI0_INTR_ENABLE(1U)

#define S_MI0_BUSY    3
#define V_MI0_BUSY(x) ((x) << S_MI0_BUSY)
#define F_MI0_BUSY    V_MI0_BUSY(1U)

#define S_MI0_MDIO    4
#define V_MI0_MDIO(x) ((x) << S_MI0_MDIO)
#define F_MI0_MDIO    V_MI0_MDIO(1U)

#define A_MI0_ADDR 0xb08

#define S_MI0_PHY_REG_ADDR    0
#define M_MI0_PHY_REG_ADDR    0x1f
#define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR)
#define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR)

#define S_MI0_PHY_ADDR    5
#define M_MI0_PHY_ADDR    0x1f
#define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR)
#define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR)

Annotation

Implementation Notes