drivers/net/ethernet/chelsio/cxgb/regs.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/chelsio/cxgb/regs.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/chelsio/cxgb/regs.h
Extension
.h
Size
73820 bytes
Lines
2159
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _CXGB_REGS_H_
#define _CXGB_REGS_H_

/* SGE registers */
#define A_SG_CONTROL 0x0

#define S_CMDQ0_ENABLE    0
#define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE)
#define F_CMDQ0_ENABLE    V_CMDQ0_ENABLE(1U)

#define S_CMDQ1_ENABLE    1
#define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE)
#define F_CMDQ1_ENABLE    V_CMDQ1_ENABLE(1U)

#define S_FL0_ENABLE    2
#define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE)
#define F_FL0_ENABLE    V_FL0_ENABLE(1U)

#define S_FL1_ENABLE    3
#define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE)
#define F_FL1_ENABLE    V_FL1_ENABLE(1U)

#define S_CPL_ENABLE    4
#define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE)
#define F_CPL_ENABLE    V_CPL_ENABLE(1U)

#define S_RESPONSE_QUEUE_ENABLE    5
#define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE)
#define F_RESPONSE_QUEUE_ENABLE    V_RESPONSE_QUEUE_ENABLE(1U)

#define S_CMDQ_PRIORITY    6
#define M_CMDQ_PRIORITY    0x3
#define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)
#define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)

#define S_DISABLE_CMDQ0_GTS    8
#define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS)
#define F_DISABLE_CMDQ0_GTS    V_DISABLE_CMDQ0_GTS(1U)

#define S_DISABLE_CMDQ1_GTS    9
#define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)
#define F_DISABLE_CMDQ1_GTS    V_DISABLE_CMDQ1_GTS(1U)

#define S_DISABLE_FL0_GTS    10
#define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS)
#define F_DISABLE_FL0_GTS    V_DISABLE_FL0_GTS(1U)

#define S_DISABLE_FL1_GTS    11
#define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS)
#define F_DISABLE_FL1_GTS    V_DISABLE_FL1_GTS(1U)

#define S_ENABLE_BIG_ENDIAN    12
#define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)
#define F_ENABLE_BIG_ENDIAN    V_ENABLE_BIG_ENDIAN(1U)

#define S_FL_SELECTION_CRITERIA    13
#define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA)
#define F_FL_SELECTION_CRITERIA    V_FL_SELECTION_CRITERIA(1U)

#define S_ISCSI_COALESCE    14
#define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)
#define F_ISCSI_COALESCE    V_ISCSI_COALESCE(1U)

#define S_RX_PKT_OFFSET    15
#define M_RX_PKT_OFFSET    0x7
#define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)
#define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET)

#define S_VLAN_XTRACT    18
#define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)
#define F_VLAN_XTRACT    V_VLAN_XTRACT(1U)

#define A_SG_DOORBELL 0x4
#define A_SG_CMD0BASELWR 0x8
#define A_SG_CMD0BASEUPR 0xc
#define A_SG_CMD1BASELWR 0x10
#define A_SG_CMD1BASEUPR 0x14
#define A_SG_FL0BASELWR 0x18
#define A_SG_FL0BASEUPR 0x1c
#define A_SG_FL1BASELWR 0x20
#define A_SG_FL1BASEUPR 0x24
#define A_SG_CMD0SIZE 0x28

#define S_CMDQ0_SIZE    0
#define M_CMDQ0_SIZE    0x1ffff
#define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE)
#define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE)

#define A_SG_FL0SIZE 0x2c

Annotation

Implementation Notes