drivers/net/ethernet/chelsio/cxgb/subr.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/chelsio/cxgb/subr.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/chelsio/cxgb/subr.c- Extension
.c- Size
- 31379 bytes
- Lines
- 1146
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
common.helmer0.hregs.hgmac.hcphy.hsge.htp.hespi.hfpga_defs.h
Detected Declarations
struct chelsio_vpd_tfunction subroutinesfunction interfacefunction t1_tpi_writefunction interfacefunction t1_tpi_readfunction t1_tpi_parfunction t1_link_changedfunction t1_pci_intr_handlerfunction fpga_phy_intr_handlerfunction for_each_portfunction fpga_slow_intrfunction mi1_wait_until_readyfunction mi1_mdio_initfunction mi1_mdio_readfunction mi1_mdio_writefunction mi1_mdio_ext_readfunction mi1_mdio_ext_writefunction t1_seeprom_readfunction t1_eeprom_vpd_getfunction vpd_macaddress_getfunction t1_link_startfunction t1_elmer0_ext_intr_handlerfunction for_each_portfunction for_each_portfunction t1_interrupts_enablefunction t1_interrupts_disablefunction t1_interrupts_clearfunction asic_slow_intrfunction t1_slow_intr_handlerfunction power_sequence_xpakfunction t1_get_board_revfunction board_initfunction t1_init_hw_modulesfunction get_pci_modefunction t1_free_sw_modulesfunction for_each_portfunction init_link_configfunction t1_init_sw_modulesfunction for_each_port
Annotated Snippet
struct chelsio_vpd_t {
u32 format_version;
u8 serial_number[16];
u8 mac_base_address[6];
u8 pad[2]; /* make multiple-of-4 size requirement explicit */
};
#define EEPROMSIZE (8 * 1024)
#define EEPROM_MAX_POLL 4
/*
* Read SEEPROM. A zero is written to the flag register when the address is
* written to the Control register. The hardware device will set the flag to a
* one when 4B have been transferred to the Data register.
*/
int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data)
{
int i = EEPROM_MAX_POLL;
u16 val;
u32 v;
if (addr >= EEPROMSIZE || (addr & 3))
return -EINVAL;
pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
do {
udelay(50);
pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
} while (!(val & F_VPD_OP_FLAG) && --i);
if (!(val & F_VPD_OP_FLAG)) {
pr_err("%s: reading EEPROM address 0x%x failed\n",
adapter->name, addr);
return -EIO;
}
pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v);
*data = cpu_to_le32(v);
return 0;
}
static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
{
int addr, ret = 0;
for (addr = 0; !ret && addr < sizeof(*vpd); addr += sizeof(u32))
ret = t1_seeprom_read(adapter, addr,
(__le32 *)((u8 *)vpd + addr));
return ret;
}
/*
* Read a port's MAC address from the VPD ROM.
*/
static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
{
struct chelsio_vpd_t vpd;
if (t1_eeprom_vpd_get(adapter, &vpd))
return 1;
memcpy(mac_addr, vpd.mac_base_address, 5);
mac_addr[5] = vpd.mac_base_address[5] + index;
return 0;
}
/*
* Set up the MAC/PHY according to the requested link settings.
*
* If the PHY can auto-negotiate first decide what to advertise, then
* enable/disable auto-negotiation as desired and reset.
*
* If the PHY does not auto-negotiate we just reset it.
*
* If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
* otherwise do it later based on the outcome of auto-negotiation.
*/
int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
{
unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
if (lc->supported & SUPPORTED_Autoneg) {
lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
if (fc) {
if (fc == ((PAUSE_RX | PAUSE_TX) &
(mac->adapter->params.nports < 2)))
lc->advertising |= ADVERTISED_PAUSE;
else {
lc->advertising |= ADVERTISED_ASYM_PAUSE;
if (fc == PAUSE_RX)
lc->advertising |= ADVERTISED_PAUSE;
Annotation
- Immediate include surface: `common.h`, `elmer0.h`, `regs.h`, `gmac.h`, `cphy.h`, `sge.h`, `tp.h`, `espi.h`.
- Detected declarations: `struct chelsio_vpd_t`, `function subroutines`, `function interface`, `function t1_tpi_write`, `function interface`, `function t1_tpi_read`, `function t1_tpi_par`, `function t1_link_changed`, `function t1_pci_intr_handler`, `function fpga_phy_intr_handler`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.