drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/chelsio/cxgb/vsc7326_reg.h
Extension
.h
Size
15557 bytes
Lines
299
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _VSC7321_REG_H_
#define _VSC7321_REG_H_

/* Register definitions for Vitesse VSC7321 (Meigs II) MAC
 *
 * Straight off the data sheet, VMDS-10038 Rev 2.0 and
 * PD0011-01-14-Meigs-II 2002-12-12
 */

/* Just 'cause it's in here doesn't mean it's used. */

#define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1))

/* System and CPU comm's registers */
#define REG_CHIP_ID		CRA(0x7,0xf,0x00)	/* Chip ID */
#define REG_BLADE_ID		CRA(0x7,0xf,0x01)	/* Blade ID */
#define REG_SW_RESET		CRA(0x7,0xf,0x02)	/* Global Soft Reset */
#define REG_MEM_BIST		CRA(0x7,0xf,0x04)	/* mem */
#define REG_IFACE_MODE		CRA(0x7,0xf,0x07)	/* Interface mode */
#define REG_MSCH		CRA(0x7,0x2,0x06)	/* CRC error count */
#define REG_CRC_CNT		CRA(0x7,0x2,0x0a)	/* CRC error count */
#define REG_CRC_CFG		CRA(0x7,0x2,0x0b)	/* CRC config */
#define REG_SI_TRANSFER_SEL	CRA(0x7,0xf,0x18)	/* SI Transfer Select */
#define REG_PLL_CLK_SPEED	CRA(0x7,0xf,0x19)	/* Clock Speed Selection */
#define REG_SYS_CLK_SELECT	CRA(0x7,0xf,0x1c)	/* System Clock Select */
#define REG_GPIO_CTRL		CRA(0x7,0xf,0x1d)	/* GPIO Control */
#define REG_GPIO_OUT		CRA(0x7,0xf,0x1e)	/* GPIO Out */
#define REG_GPIO_IN		CRA(0x7,0xf,0x1f)	/* GPIO In */
#define REG_CPU_TRANSFER_SEL	CRA(0x7,0xf,0x20)	/* CPU Transfer Select */
#define REG_LOCAL_DATA		CRA(0x7,0xf,0xfe)	/* Local CPU Data Register */
#define REG_LOCAL_STATUS	CRA(0x7,0xf,0xff)	/* Local CPU Status Register */

/* Aggregator registers */
#define REG_AGGR_SETUP		CRA(0x7,0x1,0x00)	/* Aggregator Setup */
#define REG_PMAP_TABLE		CRA(0x7,0x1,0x01)	/* Port map table */
#define REG_MPLS_BIT0		CRA(0x7,0x1,0x08)	/* MPLS bit0 position */
#define REG_MPLS_BIT1		CRA(0x7,0x1,0x09)	/* MPLS bit1 position */
#define REG_MPLS_BIT2		CRA(0x7,0x1,0x0a)	/* MPLS bit2 position */
#define REG_MPLS_BIT3		CRA(0x7,0x1,0x0b)	/* MPLS bit3 position */
#define REG_MPLS_BITMASK	CRA(0x7,0x1,0x0c)	/* MPLS bit mask */
#define REG_PRE_BIT0POS		CRA(0x7,0x1,0x10)	/* Preamble bit0 position */
#define REG_PRE_BIT1POS		CRA(0x7,0x1,0x11)	/* Preamble bit1 position */
#define REG_PRE_BIT2POS		CRA(0x7,0x1,0x12)	/* Preamble bit2 position */
#define REG_PRE_BIT3POS		CRA(0x7,0x1,0x13)	/* Preamble bit3 position */
#define REG_PRE_ERR_CNT		CRA(0x7,0x1,0x14)	/* Preamble parity error count */

/* BIST registers */
/*#define REG_RAM_BIST_CMD	CRA(0x7,0x2,0x00)*/	/* RAM BIST Command Register */
/*#define REG_RAM_BIST_RESULT	CRA(0x7,0x2,0x01)*/	/* RAM BIST Read Status/Result */
#define REG_RAM_BIST_CMD	CRA(0x7,0x1,0x00)	/* RAM BIST Command Register */
#define REG_RAM_BIST_RESULT	CRA(0x7,0x1,0x01)	/* RAM BIST Read Status/Result */
#define   BIST_PORT_SELECT	0x00			/* BIST port select */
#define   BIST_COMMAND		0x01			/* BIST enable/disable */
#define   BIST_STATUS		0x02			/* BIST operation status */
#define   BIST_ERR_CNT_LSB	0x03			/* BIST error count lo 8b */
#define   BIST_ERR_CNT_MSB	0x04			/* BIST error count hi 8b */
#define   BIST_ERR_SEL_LSB	0x05			/* BIST error select lo 8b */
#define   BIST_ERR_SEL_MSB	0x06			/* BIST error select hi 8b */
#define   BIST_ERROR_STATE	0x07			/* BIST engine internal state */
#define   BIST_ERR_ADR0		0x08			/* BIST error address lo 8b */
#define   BIST_ERR_ADR1		0x09			/* BIST error address lomid 8b */
#define   BIST_ERR_ADR2		0x0a			/* BIST error address himid 8b */
#define   BIST_ERR_ADR3		0x0b			/* BIST error address hi 8b */

/* FIFO registers
 *   ie = 0 for ingress, 1 for egress
 *   fn = FIFO number, 0-9
 */
#define REG_TEST(ie,fn)		CRA(0x2,ie&1,0x00+fn)	/* Mode & Test Register */
#define REG_TOP_BOTTOM(ie,fn)	CRA(0x2,ie&1,0x10+fn)	/* FIFO Buffer Top & Bottom */
#define REG_TAIL(ie,fn)		CRA(0x2,ie&1,0x20+fn)	/* FIFO Write Pointer */
#define REG_HEAD(ie,fn)		CRA(0x2,ie&1,0x30+fn)	/* FIFO Read Pointer */
#define REG_HIGH_LOW_WM(ie,fn)	CRA(0x2,ie&1,0x40+fn)	/* Flow Control Water Marks */
#define REG_CT_THRHLD(ie,fn)	CRA(0x2,ie&1,0x50+fn)	/* Cut Through Threshold */
#define REG_FIFO_DROP_CNT(ie,fn) CRA(0x2,ie&1,0x60+fn)	/* Drop & CRC Error Counter */
#define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn)	/* Input Side Debug Counter */
#define REG_BUCKI(fn) CRA(0x2,2,0x20+fn)	/* Input Side Debug Counter */
#define REG_BUCKE(fn) CRA(0x2,3,0x20+fn)	/* Input Side Debug Counter */

/* Traffic shaper buckets
 *   ie = 0 for ingress, 1 for egress
 *   bn = bucket number 0-10 (yes, 11 buckets)
 */
/* OK, this one's kinda ugly.  Some hardware designers are perverse. */
#define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) CRA(0x2,ie&1,0x0a + (bn>7) | ((bn&7)<<4))
#define REG_TRAFFIC_SHAPER_CONTROL(ie)	CRA(0x2,ie&1,0x3b)

#define REG_SRAM_ADR(ie)	CRA(0x2,ie&1,0x0e)	/* FIFO SRAM address */
#define REG_SRAM_WR_STRB(ie)	CRA(0x2,ie&1,0x1e)	/* FIFO SRAM write strobe */
#define REG_SRAM_RD_STRB(ie)	CRA(0x2,ie&1,0x2e)	/* FIFO SRAM read strobe */

Annotation

Implementation Notes