drivers/net/ethernet/chelsio/cxgb3/sge_defs.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/chelsio/cxgb3/sge_defs.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/chelsio/cxgb3/sge_defs.h
Extension
.h
Size
7981 bytes
Lines
257
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _SGE_DEFS_H
#define _SGE_DEFS_H

#define S_EC_CREDITS    0
#define M_EC_CREDITS    0x7FFF
#define V_EC_CREDITS(x) ((x) << S_EC_CREDITS)
#define G_EC_CREDITS(x) (((x) >> S_EC_CREDITS) & M_EC_CREDITS)

#define S_EC_GTS    15
#define V_EC_GTS(x) ((x) << S_EC_GTS)
#define F_EC_GTS    V_EC_GTS(1U)

#define S_EC_INDEX    16
#define M_EC_INDEX    0xFFFF
#define V_EC_INDEX(x) ((x) << S_EC_INDEX)
#define G_EC_INDEX(x) (((x) >> S_EC_INDEX) & M_EC_INDEX)

#define S_EC_SIZE    0
#define M_EC_SIZE    0xFFFF
#define V_EC_SIZE(x) ((x) << S_EC_SIZE)
#define G_EC_SIZE(x) (((x) >> S_EC_SIZE) & M_EC_SIZE)

#define S_EC_BASE_LO    16
#define M_EC_BASE_LO    0xFFFF
#define V_EC_BASE_LO(x) ((x) << S_EC_BASE_LO)
#define G_EC_BASE_LO(x) (((x) >> S_EC_BASE_LO) & M_EC_BASE_LO)

#define S_EC_BASE_HI    0
#define M_EC_BASE_HI    0xF
#define V_EC_BASE_HI(x) ((x) << S_EC_BASE_HI)
#define G_EC_BASE_HI(x) (((x) >> S_EC_BASE_HI) & M_EC_BASE_HI)

#define S_EC_RESPQ    4
#define M_EC_RESPQ    0x7
#define V_EC_RESPQ(x) ((x) << S_EC_RESPQ)
#define G_EC_RESPQ(x) (((x) >> S_EC_RESPQ) & M_EC_RESPQ)

#define S_EC_TYPE    7
#define M_EC_TYPE    0x7
#define V_EC_TYPE(x) ((x) << S_EC_TYPE)
#define G_EC_TYPE(x) (((x) >> S_EC_TYPE) & M_EC_TYPE)

#define S_EC_GEN    10
#define V_EC_GEN(x) ((x) << S_EC_GEN)
#define F_EC_GEN    V_EC_GEN(1U)

#define S_EC_UP_TOKEN    11
#define M_EC_UP_TOKEN    0xFFFFF
#define V_EC_UP_TOKEN(x) ((x) << S_EC_UP_TOKEN)
#define G_EC_UP_TOKEN(x) (((x) >> S_EC_UP_TOKEN) & M_EC_UP_TOKEN)

#define S_EC_VALID    31
#define V_EC_VALID(x) ((x) << S_EC_VALID)
#define F_EC_VALID    V_EC_VALID(1U)

#define S_RQ_MSI_VEC    20
#define M_RQ_MSI_VEC    0x3F
#define V_RQ_MSI_VEC(x) ((x) << S_RQ_MSI_VEC)
#define G_RQ_MSI_VEC(x) (((x) >> S_RQ_MSI_VEC) & M_RQ_MSI_VEC)

#define S_RQ_INTR_EN    26
#define V_RQ_INTR_EN(x) ((x) << S_RQ_INTR_EN)
#define F_RQ_INTR_EN    V_RQ_INTR_EN(1U)

#define S_RQ_GEN    28
#define V_RQ_GEN(x) ((x) << S_RQ_GEN)
#define F_RQ_GEN    V_RQ_GEN(1U)

#define S_CQ_INDEX    0
#define M_CQ_INDEX    0xFFFF
#define V_CQ_INDEX(x) ((x) << S_CQ_INDEX)
#define G_CQ_INDEX(x) (((x) >> S_CQ_INDEX) & M_CQ_INDEX)

#define S_CQ_SIZE    16
#define M_CQ_SIZE    0xFFFF
#define V_CQ_SIZE(x) ((x) << S_CQ_SIZE)
#define G_CQ_SIZE(x) (((x) >> S_CQ_SIZE) & M_CQ_SIZE)

#define S_CQ_BASE_HI    0
#define M_CQ_BASE_HI    0xFFFFF
#define V_CQ_BASE_HI(x) ((x) << S_CQ_BASE_HI)
#define G_CQ_BASE_HI(x) (((x) >> S_CQ_BASE_HI) & M_CQ_BASE_HI)

#define S_CQ_RSPQ    20
#define M_CQ_RSPQ    0x3F
#define V_CQ_RSPQ(x) ((x) << S_CQ_RSPQ)
#define G_CQ_RSPQ(x) (((x) >> S_CQ_RSPQ) & M_CQ_RSPQ)

#define S_CQ_ASYNC_NOTIF    26
#define V_CQ_ASYNC_NOTIF(x) ((x) << S_CQ_ASYNC_NOTIF)

Annotation

Implementation Notes