drivers/net/ethernet/chelsio/cxgb4/cudbg_zlib.h

File Facts

System

Linux kernel

Corpus path

drivers/net/ethernet/chelsio/cxgb4/cudbg_zlib.h

Extension

.h

Size

691 bytes

Lines

32

Domain

Driver Families

Bucket

drivers/net

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/zlib.h

Detected Declarations

• struct cudbg_compress_hdr
• function cudbg_get_workspace_size

Annotated Snippet

struct cudbg_compress_hdr {
	u32 compress_id;
	u64 decompress_size;
	u64 compress_size;
	u64 rsvd[32];
};

static inline int cudbg_get_workspace_size(void)
{
	return zlib_deflate_workspacesize(CUDBG_ZLIB_WIN_BITS,
					  CUDBG_ZLIB_MEM_LVL);
}

int cudbg_compress_buff(struct cudbg_init *pdbg_init,
			struct cudbg_buffer *pin_buff,
			struct cudbg_buffer *pout_buff);
#endif /* __CUDBG_ZLIB_H__ */

Annotation

• Immediate include surface: `linux/zlib.h`.
• Detected declarations: `struct cudbg_compress_hdr`, `function cudbg_get_workspace_size`.
• Atlas domain: Driver Families / drivers/net.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.