drivers/net/ethernet/chelsio/cxgb4/srq.h

File Facts

System

Linux kernel

Corpus path

drivers/net/ethernet/chelsio/cxgb4/srq.h

Extension

.h

Size

2049 bytes

Lines

64

Domain

Driver Families

Bucket

drivers/net

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• struct adapter
• struct cpl_srq_table_rpl
• struct srq_entry
• struct srq_data

Annotated Snippet

struct srq_entry {
	u8 valid;
	u8 idx;
	u8 qlen;
	u16 pdid;
	u16 cur_msn;
	u16 max_msn;
	u32 qbase;
};

struct srq_data {
	unsigned int srq_size;
	struct srq_entry *entryp;
	struct completion comp;
	struct mutex lock; /* generic mutex for srq data */
};

struct srq_data *t4_init_srq(int srq_size);
void do_srq_table_rpl(struct adapter *adap,
		      const struct cpl_srq_table_rpl *rpl);
#endif  /* __CXGB4_SRQ_H */

Annotation

• Detected declarations: `struct adapter`, `struct cpl_srq_table_rpl`, `struct srq_entry`, `struct srq_data`.
• Atlas domain: Driver Families / drivers/net.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.