drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h- Extension
.h- Size
- 101698 bytes
- Lines
- 3387
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __T4_REGS_H
#define __T4_REGS_H
#define MYPF_BASE 0x1b000
#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
#define PF0_BASE 0x1e000
#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
#define PF_STRIDE 0x400
#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
#define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
#define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
#define MYPORT_BASE 0x1c000
#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
#define PORT0_BASE 0x20000
#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
#define PORT_STRIDE 0x2000
#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
#define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17
#define SGE_PF_KDOORBELL_A 0x0
#define QID_S 15
#define QID_V(x) ((x) << QID_S)
#define DBPRIO_S 14
#define DBPRIO_V(x) ((x) << DBPRIO_S)
#define DBPRIO_F DBPRIO_V(1U)
#define PIDX_S 0
#define PIDX_V(x) ((x) << PIDX_S)
#define SGE_VF_KDOORBELL_A 0x0
#define DBTYPE_S 13
#define DBTYPE_V(x) ((x) << DBTYPE_S)
#define DBTYPE_F DBTYPE_V(1U)
#define PIDX_T5_S 0
#define PIDX_T5_M 0x1fffU
#define PIDX_T5_V(x) ((x) << PIDX_T5_S)
#define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M)
#define SGE_PF_GTS_A 0x4
#define INGRESSQID_S 16
#define INGRESSQID_V(x) ((x) << INGRESSQID_S)
#define TIMERREG_S 13
#define TIMERREG_V(x) ((x) << TIMERREG_S)
#define SEINTARM_S 12
#define SEINTARM_V(x) ((x) << SEINTARM_S)
#define CIDXINC_S 0
#define CIDXINC_M 0xfffU
#define CIDXINC_V(x) ((x) << CIDXINC_S)
#define SGE_CONTROL_A 0x1008
#define SGE_CONTROL2_A 0x1124
#define RXPKTCPLMODE_S 18
#define RXPKTCPLMODE_V(x) ((x) << RXPKTCPLMODE_S)
#define RXPKTCPLMODE_F RXPKTCPLMODE_V(1U)
#define EGRSTATUSPAGESIZE_S 17
#define EGRSTATUSPAGESIZE_V(x) ((x) << EGRSTATUSPAGESIZE_S)
#define EGRSTATUSPAGESIZE_F EGRSTATUSPAGESIZE_V(1U)
#define PKTSHIFT_S 10
#define PKTSHIFT_M 0x7U
Annotation
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.