drivers/net/ethernet/chelsio/cxgb4vf/adapter.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/chelsio/cxgb4vf/adapter.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/chelsio/cxgb4vf/adapter.h- Extension
.h- Size
- 17819 bytes
- Lines
- 578
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/etherdevice.hlinux/interrupt.hlinux/pci.hlinux/spinlock.hlinux/skbuff.hlinux/if_ether.hlinux/netdevice.h../cxgb4/t4_hw.h
Detected Declarations
struct adapterstruct sge_eth_rxqstruct sge_rspqstruct port_infostruct rx_sw_descstruct sge_flstruct pkt_glstruct sge_rspqstruct sge_eth_statsstruct sge_eth_rxqstruct tx_descstruct tx_sw_descstruct sge_txqstruct sge_eth_txqstruct sgestruct hash_mac_addrstruct mbox_liststruct adapterfunction t4_read_regfunction t4_write_regfunction readqfunction writeqfunction t4_read_reg64function t4_write_reg64function t4_os_set_hw_addr
Annotated Snippet
struct port_info {
struct adapter *adapter; /* our adapter */
u32 vlan_id; /* vlan id for VST */
u16 viid; /* virtual interface ID */
int xact_addr_filt; /* index of our MAC address filter */
u16 rss_size; /* size of VI's RSS table slice */
u8 pidx; /* index into adapter port[] */
s8 mdio_addr;
u8 port_type; /* firmware port type */
u8 mod_type; /* firmware module type */
u8 port_id; /* physical port ID */
u8 nqsets; /* # of "Queue Sets" */
u8 first_qset; /* index of first "Queue Set" */
struct link_config link_cfg; /* physical port configuration */
};
/*
* Scatter Gather Engine resources for the "adapter". Our ingress and egress
* queues are organized into "Queue Sets" with one ingress and one egress
* queue per Queue Set. These Queue Sets are aportionable between the "ports"
* (Virtual Interfaces). One extra ingress queue is used to receive
* asynchronous messages from the firmware. Note that the "Queue IDs" that we
* use here are really "Relative Queue IDs" which are returned as part of the
* firmware command to allocate queues. These queue IDs are relative to the
* absolute Queue ID base of the section of the Queue ID space allocated to
* the PF/VF.
*/
/*
* SGE free-list queue state.
*/
struct rx_sw_desc;
struct sge_fl {
unsigned int avail; /* # of available RX buffers */
unsigned int pend_cred; /* new buffers since last FL DB ring */
unsigned int cidx; /* consumer index */
unsigned int pidx; /* producer index */
unsigned long alloc_failed; /* # of buffer allocation failures */
unsigned long large_alloc_failed;
unsigned long starving; /* # of times FL was found starving */
/*
* Write-once/infrequently fields.
* -------------------------------
*/
unsigned int cntxt_id; /* SGE relative QID for the free list */
unsigned int abs_id; /* SGE absolute QID for the free list */
unsigned int size; /* capacity of free list */
struct rx_sw_desc *sdesc; /* address of SW RX descriptor ring */
__be64 *desc; /* address of HW RX descriptor ring */
dma_addr_t addr; /* PCI bus address of hardware ring */
void __iomem *bar2_addr; /* address of BAR2 Queue registers */
unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
};
/*
* An ingress packet gather list.
*/
struct pkt_gl {
struct page_frag frags[MAX_SKB_FRAGS];
void *va; /* virtual address of first byte */
unsigned int nfrags; /* # of fragments */
unsigned int tot_len; /* total length of fragments */
};
typedef int (*rspq_handler_t)(struct sge_rspq *, const __be64 *,
const struct pkt_gl *);
/*
* State for an SGE Response Queue.
*/
struct sge_rspq {
struct napi_struct napi; /* NAPI scheduling control */
const __be64 *cur_desc; /* current descriptor in queue */
unsigned int cidx; /* consumer index */
u8 gen; /* current generation bit */
u8 next_intr_params; /* holdoff params for next interrupt */
int offset; /* offset into current FL buffer */
unsigned int unhandled_irqs; /* bogus interrupts */
/*
* Write-once/infrequently fields.
* -------------------------------
*/
u8 intr_params; /* interrupt holdoff parameters */
u8 pktcnt_idx; /* interrupt packet threshold */
u8 idx; /* queue index within its group */
Annotation
- Immediate include surface: `linux/etherdevice.h`, `linux/interrupt.h`, `linux/pci.h`, `linux/spinlock.h`, `linux/skbuff.h`, `linux/if_ether.h`, `linux/netdevice.h`, `../cxgb4/t4_hw.h`.
- Detected declarations: `struct adapter`, `struct sge_eth_rxq`, `struct sge_rspq`, `struct port_info`, `struct rx_sw_desc`, `struct sge_fl`, `struct pkt_gl`, `struct sge_rspq`, `struct sge_eth_stats`, `struct sge_eth_rxq`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.