drivers/net/ethernet/cisco/enic/cq_enet_desc.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/cisco/enic/cq_enet_desc.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/cisco/enic/cq_enet_desc.h- Extension
.h- Size
- 4604 bytes
- Lines
- 141
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
cq_desc.h
Detected Declarations
struct cq_enet_wq_descstruct cq_enet_rq_descstruct cq_enet_rq_desc_32struct cq_enet_rq_desc_64
Annotated Snippet
struct cq_enet_wq_desc {
__le16 completed_index;
__le16 q_number;
u8 reserved[11];
u8 type_color;
};
/*
* Defines and Capabilities for CMD_CQ_ENTRY_SIZE_SET
*/
#define VNIC_RQ_ALL (~0ULL)
#define VNIC_RQ_CQ_ENTRY_SIZE_16 0
#define VNIC_RQ_CQ_ENTRY_SIZE_32 1
#define VNIC_RQ_CQ_ENTRY_SIZE_64 2
#define VNIC_RQ_CQ_ENTRY_SIZE_16_CAPABLE BIT(VNIC_RQ_CQ_ENTRY_SIZE_16)
#define VNIC_RQ_CQ_ENTRY_SIZE_32_CAPABLE BIT(VNIC_RQ_CQ_ENTRY_SIZE_32)
#define VNIC_RQ_CQ_ENTRY_SIZE_64_CAPABLE BIT(VNIC_RQ_CQ_ENTRY_SIZE_64)
#define VNIC_RQ_CQ_ENTRY_SIZE_ALL_BIT (VNIC_RQ_CQ_ENTRY_SIZE_16_CAPABLE | \
VNIC_RQ_CQ_ENTRY_SIZE_32_CAPABLE | \
VNIC_RQ_CQ_ENTRY_SIZE_64_CAPABLE)
/* Completion queue descriptor: Ethernet receive queue, 16B */
struct cq_enet_rq_desc {
__le16 completed_index_flags;
__le16 q_number_rss_type_flags;
__le32 rss_hash;
__le16 bytes_written_flags;
__le16 vlan;
__le16 checksum_fcoe;
u8 flags;
u8 type_color;
};
/* Completion queue descriptor: Ethernet receive queue, 32B */
struct cq_enet_rq_desc_32 {
__le16 completed_index_flags;
__le16 q_number_rss_type_flags;
__le32 rss_hash;
__le16 bytes_written_flags;
__le16 vlan;
__le16 checksum_fcoe;
u8 flags;
u8 fetch_index_flags;
__le32 time_stamp;
__le16 time_stamp2;
__le16 pie_info;
__le32 pie_info2;
__le16 pie_info3;
u8 pie_info4;
u8 type_color;
};
/* Completion queue descriptor: Ethernet receive queue, 64B */
struct cq_enet_rq_desc_64 {
__le16 completed_index_flags;
__le16 q_number_rss_type_flags;
__le32 rss_hash;
__le16 bytes_written_flags;
__le16 vlan;
__le16 checksum_fcoe;
u8 flags;
u8 fetch_index_flags;
__le32 time_stamp;
__le16 time_stamp2;
__le16 pie_info;
__le32 pie_info2;
__le16 pie_info3;
u8 pie_info4;
u8 reserved[32];
u8 type_color;
};
#define CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT (0x1 << 12)
#define CQ_ENET_RQ_DESC_FLAGS_FCOE (0x1 << 13)
#define CQ_ENET_RQ_DESC_FLAGS_EOP (0x1 << 14)
#define CQ_ENET_RQ_DESC_FLAGS_SOP (0x1 << 15)
#define CQ_ENET_RQ_DESC_RSS_TYPE_BITS 4
#define CQ_ENET_RQ_DESC_RSS_TYPE_MASK \
((1 << CQ_ENET_RQ_DESC_RSS_TYPE_BITS) - 1)
#define CQ_ENET_RQ_DESC_RSS_TYPE_NONE 0
#define CQ_ENET_RQ_DESC_RSS_TYPE_IPv4 1
#define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv4 2
#define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6 3
#define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6 4
#define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6_EX 5
#define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6_EX 6
Annotation
- Immediate include surface: `cq_desc.h`.
- Detected declarations: `struct cq_enet_wq_desc`, `struct cq_enet_rq_desc`, `struct cq_enet_rq_desc_32`, `struct cq_enet_rq_desc_64`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.