drivers/net/ethernet/davicom/dm9051.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/davicom/dm9051.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/davicom/dm9051.c- Extension
.c- Size
- 29279 bytes
- Lines
- 1259
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/etherdevice.hlinux/ethtool.hlinux/interrupt.hlinux/iopoll.hlinux/irq.hlinux/mii.hlinux/module.hlinux/netdevice.hlinux/phy.hlinux/regmap.hlinux/skbuff.hlinux/spinlock.hlinux/spi/spi.hlinux/types.hdm9051.h
Detected Declarations
struct rx_ctl_machstruct dm9051_rxctrlstruct dm9051_rxhdrstruct board_infofunction dm9051_set_regfunction dm9051_update_bitsfunction dm9051_dumpblkfunction dm9051_set_regsfunction dm9051_get_regsfunction dm9051_write_memfunction dm9051_read_memfunction dm9051_nsr_pollfunction dm9051_epcr_pollfunction dm9051_irq_flagfunction dm9051_intcr_valuefunction dm9051_set_fcrfunction dm9051_set_recvfunction dm9051_core_resetfunction dm9051_update_fcrfunction dm9051_disable_interruptfunction dm9051_enable_interruptfunction dm9051_stop_mrcmdfunction dm9051_clear_interruptfunction dm9051_eeprom_readfunction dm9051_eeprom_writefunction dm9051_phyreadfunction dm9051_phywritefunction dm9051_mdio_readfunction dm9051_mdio_writefunction dm9051_reg_lock_mutexfunction dm9051_reg_unlock_mutexfunction dm9051_map_initfunction dm9051_map_chipidfunction dm9051_map_etherdev_parfunction dm9051_get_drvinfofunction dm9051_set_msglevelfunction dm9051_get_msglevelfunction dm9051_get_eeprom_lenfunction dm9051_get_eepromfunction dm9051_set_eepromfunction dm9051_get_pauseparamfunction dm9051_set_pauseparamfunction dm9051_all_startfunction dm9051_all_stopfunction dm9051_all_restartfunction dm9051_loop_rxfunction dm9051_single_txfunction dm9051_loop_tx
Annotated Snippet
static const struct net_device_ops dm9051_netdev_ops = {
.ndo_open = dm9051_open,
.ndo_stop = dm9051_stop,
.ndo_start_xmit = dm9051_start_xmit,
.ndo_set_rx_mode = dm9051_set_rx_mode,
.ndo_validate_addr = eth_validate_addr,
.ndo_set_mac_address = dm9051_set_mac_address,
};
static void dm9051_operation_clear(struct board_info *db)
{
db->bc.status_err_counter = 0;
db->bc.large_err_counter = 0;
db->bc.rx_err_counter = 0;
db->bc.tx_err_counter = 0;
db->bc.fifo_rst_counter = 0;
}
static int dm9051_mdio_register(struct board_info *db)
{
struct spi_device *spi = db->spidev;
int ret;
db->mdiobus = devm_mdiobus_alloc(&spi->dev);
if (!db->mdiobus)
return -ENOMEM;
db->mdiobus->priv = db;
db->mdiobus->read = dm9051_mdio_read;
db->mdiobus->write = dm9051_mdio_write;
db->mdiobus->name = "dm9051-mdiobus";
db->mdiobus->phy_mask = (u32)~BIT(1);
db->mdiobus->parent = &spi->dev;
snprintf(db->mdiobus->id, MII_BUS_ID_SIZE,
"dm9051-%s.%u", dev_name(&spi->dev), spi_get_chipselect(spi, 0));
ret = devm_mdiobus_register(&spi->dev, db->mdiobus);
if (ret)
dev_err(&spi->dev, "Could not register MDIO bus\n");
return ret;
}
static void dm9051_handle_link_change(struct net_device *ndev)
{
struct board_info *db = to_dm9051_board(ndev);
phy_print_status(db->phydev);
/* only write pause settings to mac. since mac and phy are integrated
* together, such as link state, speed and duplex are sync already
*/
if (db->phydev->link) {
if (db->phydev->pause) {
db->pause.rx_pause = true;
db->pause.tx_pause = true;
}
dm9051_update_fcr(db);
}
}
/* phy connect as poll mode
*/
static int dm9051_phy_connect(struct board_info *db)
{
char phy_id[MII_BUS_ID_SIZE + 3];
snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
db->mdiobus->id, DM9051_PHY_ADDR);
db->phydev = phy_connect(db->ndev, phy_id, dm9051_handle_link_change,
PHY_INTERFACE_MODE_MII);
return PTR_ERR_OR_ZERO(db->phydev);
}
static int dm9051_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
struct net_device *ndev;
struct board_info *db;
int ret;
ndev = devm_alloc_etherdev(dev, sizeof(struct board_info));
if (!ndev)
return -ENOMEM;
SET_NETDEV_DEV(ndev, dev);
dev_set_drvdata(dev, ndev);
db = netdev_priv(ndev);
Annotation
- Immediate include surface: `linux/etherdevice.h`, `linux/ethtool.h`, `linux/interrupt.h`, `linux/iopoll.h`, `linux/irq.h`, `linux/mii.h`, `linux/module.h`, `linux/netdevice.h`.
- Detected declarations: `struct rx_ctl_mach`, `struct dm9051_rxctrl`, `struct dm9051_rxhdr`, `struct board_info`, `function dm9051_set_reg`, `function dm9051_update_bits`, `function dm9051_dumpblk`, `function dm9051_set_regs`, `function dm9051_get_regs`, `function dm9051_write_mem`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.