drivers/net/ethernet/dec/tulip/dmfe.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/dec/tulip/dmfe.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/dec/tulip/dmfe.c- Extension
.c- Size
- 59105 bytes
- Lines
- 2219
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/kernel.hlinux/string.hlinux/timer.hlinux/ptrace.hlinux/errno.hlinux/ioport.hlinux/interrupt.hlinux/pci.hlinux/dma-mapping.hlinux/init.hlinux/netdevice.hlinux/etherdevice.hlinux/ethtool.hlinux/skbuff.hlinux/delay.hlinux/spinlock.hlinux/crc32.hlinux/bitops.hasm/processor.hasm/io.hasm/dma.hlinux/uaccess.hasm/irq.hlinux/of.h
Detected Declarations
struct tx_descstruct rx_descstruct dmfe_board_infoenum dmfe_offsetsenum dmfe_CR6_bitsfunction dmfe_init_onefunction dmfe_remove_onefunction dmfe_openfunction dmfe_init_dm910xfunction dmfe_start_xmitfunction dmfe_stopfunction dmfe_interruptfunction poll_dmfefunction dmfe_free_tx_pktfunction cal_CRCfunction dmfe_rx_packetfunction dmfe_set_filter_modefunction dmfe_ethtool_get_drvinfofunction dmfe_ethtool_set_wolfunction dmfe_ethtool_get_wolfunction dmfe_timerfunction time_afterfunction dmfe_dynamic_resetfunction dmfe_free_rxbufferfunction dmfe_reuse_skbfunction dmfe_descriptor_initfunction update_cr6function dm9132_id_tablefunction send_filter_framefunction allocate_rx_bufferfunction srom_clk_writefunction read_srom_wordfunction dmfe_sense_speedfunction dmfe_set_phyxcerfunction dmfe_process_modefunction dmfe_phy_writefunction dmfe_phy_readfunction dmfe_phy_write_1bitfunction dmfe_phy_read_1bitfunction dmfe_parse_sromfunction dmfe_program_DM9801function dmfe_program_DM9802function dmfe_HPNA_remote_cmd_chkfunction dmfe_suspendfunction dmfe_resumefunction dmfe_init_modulefunction dmfe_cleanup_modulemodule init dmfe_init_module
Annotated Snippet
static const struct net_device_ops netdev_ops = {
.ndo_open = dmfe_open,
.ndo_stop = dmfe_stop,
.ndo_start_xmit = dmfe_start_xmit,
.ndo_set_rx_mode = dmfe_set_filter_mode,
.ndo_set_mac_address = eth_mac_addr,
.ndo_validate_addr = eth_validate_addr,
#ifdef CONFIG_NET_POLL_CONTROLLER
.ndo_poll_controller = poll_dmfe,
#endif
};
/*
* Search DM910X board ,allocate space and register it
*/
static int dmfe_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct dmfe_board_info *db; /* board information structure */
struct net_device *dev;
u32 pci_pmr;
int i, err;
DMFE_DBUG(0, "dmfe_init_one()", 0);
/*
* SPARC on-board DM910x chips should be handled by the main
* tulip driver, except for early DM9100s.
*/
#ifdef CONFIG_TULIP_DM910X
if ((ent->driver_data == PCI_DM9100_ID && pdev->revision >= 0x30) ||
ent->driver_data == PCI_DM9102_ID) {
struct device_node *dp = pci_device_to_OF_node(pdev);
if (dp && of_get_property(dp, "local-mac-address", NULL)) {
pr_info("skipping on-board DM910x (use tulip)\n");
return -ENODEV;
}
}
#endif
/* Init network device */
dev = alloc_etherdev(sizeof(*db));
if (dev == NULL)
return -ENOMEM;
SET_NETDEV_DEV(dev, &pdev->dev);
if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
pr_warn("32-bit PCI DMA not available\n");
err = -ENODEV;
goto err_out_free;
}
/* Enable Master/IO access, Disable memory access */
err = pci_enable_device(pdev);
if (err)
goto err_out_free;
if (!pci_resource_start(pdev, 0)) {
pr_err("I/O base is zero\n");
err = -ENODEV;
goto err_out_disable;
}
if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
pr_err("Allocated I/O size too small\n");
err = -ENODEV;
goto err_out_disable;
}
#if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
/* Set Latency Timer 80h */
/* FIXME: setting values > 32 breaks some SiS 559x stuff.
Need a PCI quirk.. */
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
#endif
if (pci_request_regions(pdev, DRV_NAME)) {
pr_err("Failed to request PCI regions\n");
err = -ENODEV;
goto err_out_disable;
}
/* Init system & device */
db = netdev_priv(dev);
/* Allocate Tx/Rx descriptor memory */
db->desc_pool_ptr = dma_alloc_coherent(&pdev->dev,
Annotation
- Immediate include surface: `linux/module.h`, `linux/kernel.h`, `linux/string.h`, `linux/timer.h`, `linux/ptrace.h`, `linux/errno.h`, `linux/ioport.h`, `linux/interrupt.h`.
- Detected declarations: `struct tx_desc`, `struct rx_desc`, `struct dmfe_board_info`, `enum dmfe_offsets`, `enum dmfe_CR6_bits`, `function dmfe_init_one`, `function dmfe_remove_one`, `function dmfe_open`, `function dmfe_init_dm910x`, `function dmfe_start_xmit`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.