drivers/net/ethernet/emulex/benet/be_cmds.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/emulex/benet/be_cmds.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/emulex/benet/be_cmds.h
Extension
.h
Size
64188 bytes
Lines
2509
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct be_sge {
	u32 pa_lo;
	u32 pa_hi;
	u32 len;
};

#define MCC_WRB_EMBEDDED_MASK	1 	/* bit 0 of dword 0*/
#define MCC_WRB_SGE_CNT_SHIFT	3	/* bits 3 - 7 of dword 0 */
#define MCC_WRB_SGE_CNT_MASK	0x1F	/* bits 3 - 7 of dword 0 */
struct be_mcc_wrb {
	u32 embedded;		/* dword 0 */
	u32 payload_length;	/* dword 1 */
	u32 tag0;		/* dword 2 */
	u32 tag1;		/* dword 3 */
	u32 rsvd;		/* dword 4 */
	union {
		u8 embedded_payload[236]; /* used by embedded cmds */
		struct be_sge sgl[19];    /* used by non-embedded cmds */
	} payload;
};

#define CQE_FLAGS_VALID_MASK		BIT(31)
#define CQE_FLAGS_ASYNC_MASK		BIT(30)
#define CQE_FLAGS_COMPLETED_MASK	BIT(28)
#define CQE_FLAGS_CONSUMED_MASK		BIT(27)

/* Completion Status */
enum mcc_base_status {
	MCC_STATUS_SUCCESS = 0,
	MCC_STATUS_FAILED = 1,
	MCC_STATUS_ILLEGAL_REQUEST = 2,
	MCC_STATUS_ILLEGAL_FIELD = 3,
	MCC_STATUS_INSUFFICIENT_BUFFER = 4,
	MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
	MCC_STATUS_NOT_SUPPORTED = 66,
	MCC_STATUS_FEATURE_NOT_SUPPORTED = 68,
	MCC_STATUS_INVALID_LENGTH = 116
};

/* Additional status */
enum mcc_addl_status {
	MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16,
	MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d,
	MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a,
	MCC_ADDL_STATUS_INSUFFICIENT_VLANS = 0xab,
	MCC_ADDL_STATUS_INVALID_SIGNATURE = 0x56,
	MCC_ADDL_STATUS_MISSING_SIGNATURE = 0x57,
	MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES = 0x60
};

#define CQE_BASE_STATUS_MASK		0xFFFF
#define CQE_BASE_STATUS_SHIFT		0	/* bits 0 - 15 */
#define CQE_ADDL_STATUS_MASK		0xFF
#define CQE_ADDL_STATUS_SHIFT		16	/* bits 16 - 31 */

#define base_status(status)		\
		((enum mcc_base_status)	\
			(status > 0 ? (status & CQE_BASE_STATUS_MASK) : 0))
#define addl_status(status)		\
		((enum mcc_addl_status)	\
			(status > 0 ? (status >> CQE_ADDL_STATUS_SHIFT) & \
					CQE_ADDL_STATUS_MASK : 0))

struct be_mcc_compl {
	u32 status;		/* dword 0 */
	u32 tag0;		/* dword 1 */
	u32 tag1;		/* dword 2 */
	u32 flags;		/* dword 3 */
};

/* When the async bit of mcc_compl flags is set, flags
 * is interpreted as follows:
 */
#define ASYNC_EVENT_CODE_SHIFT		8	/* bits 8 - 15 */
#define ASYNC_EVENT_CODE_MASK		0xFF
#define ASYNC_EVENT_TYPE_SHIFT		16
#define ASYNC_EVENT_TYPE_MASK		0xFF
#define ASYNC_EVENT_CODE_LINK_STATE	0x1
#define ASYNC_EVENT_CODE_GRP_5		0x5
#define ASYNC_EVENT_QOS_SPEED		0x1
#define ASYNC_EVENT_COS_PRIORITY	0x2
#define ASYNC_EVENT_PVID_STATE		0x3
#define ASYNC_EVENT_CODE_QNQ		0x6
#define ASYNC_DEBUG_EVENT_TYPE_QNQ	1
#define ASYNC_EVENT_CODE_SLIPORT	0x11
#define ASYNC_EVENT_PORT_MISCONFIG	0x9
#define ASYNC_EVENT_FW_CONTROL		0x5

enum {
	LINK_DOWN	= 0x0,

Annotation

Implementation Notes