drivers/net/ethernet/emulex/benet/be_hw.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/emulex/benet/be_hw.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/emulex/benet/be_hw.h
Extension
.h
Size
11832 bytes
Lines
372
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct be_eq_entry {
	u32 evt;
};

/* TX Queue Descriptor */
#define ETH_WRB_FRAG_LEN_MASK		0xFFFF
struct be_eth_wrb {
	__le32 frag_pa_hi;		/* dword 0 */
	__le32 frag_pa_lo;		/* dword 1 */
	u32 rsvd0;			/* dword 2 */
	__le32 frag_len;		/* dword 3: bits 0 - 15 */
} __packed;

/* Pseudo amap definition for eth_hdr_wrb in which each bit of the
 * actual structure is defined as a byte : used to calculate
 * offset/shift/mask of each field */
struct amap_eth_hdr_wrb {
	u8 rsvd0[32];		/* dword 0 */
	u8 rsvd1[32];		/* dword 1 */
	u8 complete;		/* dword 2 */
	u8 event;
	u8 crc;
	u8 forward;
	u8 lso6;
	u8 mgmt;
	u8 ipcs;
	u8 udpcs;
	u8 tcpcs;
	u8 lso;
	u8 vlan;
	u8 gso[2];
	u8 num_wrb[5];
	u8 lso_mss[14];
	u8 len[16];		/* dword 3 */
	u8 vlan_tag[16];
} __packed;

#define TX_HDR_WRB_COMPL		1		/* word 2 */
#define TX_HDR_WRB_EVT			BIT(1)		/* word 2 */
#define TX_HDR_WRB_NUM_SHIFT		13		/* word 2: bits 13:17 */
#define TX_HDR_WRB_NUM_MASK		0x1F		/* word 2: bits 13:17 */

struct be_eth_hdr_wrb {
	__le32 dw[4];
};

/********* Tx Compl Status Encoding *********/
#define BE_TX_COMP_HDR_PARSE_ERR	0x2
#define BE_TX_COMP_NDMA_ERR		0x3
#define BE_TX_COMP_ACL_ERR		0x5

#define LANCER_TX_COMP_LSO_ERR			0x1
#define LANCER_TX_COMP_HSW_DROP_MAC_ERR		0x3
#define LANCER_TX_COMP_HSW_DROP_VLAN_ERR	0x5
#define LANCER_TX_COMP_QINQ_ERR			0x7
#define LANCER_TX_COMP_SGE_ERR			0x9
#define LANCER_TX_COMP_PARITY_ERR		0xb
#define LANCER_TX_COMP_DMA_ERR			0xd

/* TX Compl Queue Descriptor */

/* Pseudo amap definition for eth_tx_compl in which each bit of the
 * actual structure is defined as a byte: used to calculate
 * offset/shift/mask of each field */
struct amap_eth_tx_compl {
	u8 wrb_index[16];	/* dword 0 */
	u8 ct[2]; 		/* dword 0 */
	u8 port[2];		/* dword 0 */
	u8 rsvd0[8];		/* dword 0 */
	u8 status[4];		/* dword 0 */
	u8 user_bytes[16];	/* dword 1 */
	u8 nwh_bytes[8];	/* dword 1 */
	u8 lso;			/* dword 1 */
	u8 cast_enc[2];		/* dword 1 */
	u8 rsvd1[5];		/* dword 1 */
	u8 rsvd2[32];		/* dword 2 */
	u8 pkts[16];		/* dword 3 */
	u8 ringid[11];		/* dword 3 */
	u8 hash_val[4];		/* dword 3 */
	u8 valid;		/* dword 3 */
} __packed;

struct be_eth_tx_compl {
	u32 dw[4];
};

/* RX Queue Descriptor */
struct be_eth_rx_d {
	u32 fragpa_hi;
	u32 fragpa_lo;

Annotation

Implementation Notes