drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c- Extension
.c- Size
- 24131 bytes
- Lines
- 892
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dpaa2-switch.h
Detected Declarations
function dpaa2_switch_flower_parse_keyfunction dpaa2_switch_acl_entry_addfunction dpaa2_switch_acl_entry_removefunction dpaa2_switch_acl_entry_add_to_listfunction list_for_each_safefunction dpaa2_switch_acl_entry_get_by_indexfunction list_for_each_entryfunction dpaa2_switch_acl_entry_set_precedencefunction dpaa2_switch_acl_tbl_add_entryfunction dpaa2_switch_acl_tbl_find_entry_by_cookiefunction list_for_each_entry_safefunction dpaa2_switch_acl_entry_get_indexfunction list_for_each_entry_safefunction dpaa2_switch_mirror_find_entry_by_cookiefunction list_for_each_entry_safefunction dpaa2_switch_acl_tbl_remove_entryfunction dpaa2_switch_tc_parse_action_aclfunction dpaa2_switch_block_add_mirrorfunction dpaa2_switch_block_remove_mirrorfunction dpaa2_switch_cls_flower_replace_aclfunction dpaa2_switch_flower_parse_mirror_keyfunction dpaa2_switch_cls_flower_replace_mirrorfunction dpaa2_switch_cls_flower_replacefunction dpaa2_switch_cls_flower_destroyfunction dpaa2_switch_cls_matchall_replace_aclfunction dpaa2_switch_cls_matchall_replace_mirrorfunction dpaa2_switch_cls_matchall_replacefunction dpaa2_switch_block_offload_mirrorfunction list_for_each_entryfunction dpaa2_switch_block_unoffload_mirrorfunction list_for_each_entryfunction dpaa2_switch_cls_matchall_destroy
Annotated Snippet
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS))) {
NL_SET_ERR_MSG_MOD(extack,
"Unsupported keys used");
return -EOPNOTSUPP;
}
acl_h = &acl_key->match;
acl_m = &acl_key->mask;
if (flow_rule_match_has_control_flags(rule, extack))
return -EOPNOTSUPP;
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
struct flow_match_basic match;
flow_rule_match_basic(rule, &match);
acl_h->l3_protocol = match.key->ip_proto;
acl_h->l2_ether_type = be16_to_cpu(match.key->n_proto);
acl_m->l3_protocol = match.mask->ip_proto;
acl_m->l2_ether_type = be16_to_cpu(match.mask->n_proto);
}
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
struct flow_match_eth_addrs match;
flow_rule_match_eth_addrs(rule, &match);
ether_addr_copy(acl_h->l2_dest_mac, &match.key->dst[0]);
ether_addr_copy(acl_h->l2_source_mac, &match.key->src[0]);
ether_addr_copy(acl_m->l2_dest_mac, &match.mask->dst[0]);
ether_addr_copy(acl_m->l2_source_mac, &match.mask->src[0]);
}
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
struct flow_match_vlan match;
flow_rule_match_vlan(rule, &match);
acl_h->l2_vlan_id = match.key->vlan_id;
acl_h->l2_tpid = be16_to_cpu(match.key->vlan_tpid);
acl_h->l2_pcp_dei = match.key->vlan_priority << 1 |
match.key->vlan_dei;
acl_m->l2_vlan_id = match.mask->vlan_id;
acl_m->l2_tpid = be16_to_cpu(match.mask->vlan_tpid);
acl_m->l2_pcp_dei = match.mask->vlan_priority << 1 |
match.mask->vlan_dei;
}
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IPV4_ADDRS)) {
struct flow_match_ipv4_addrs match;
flow_rule_match_ipv4_addrs(rule, &match);
acl_h->l3_source_ip = be32_to_cpu(match.key->src);
acl_h->l3_dest_ip = be32_to_cpu(match.key->dst);
acl_m->l3_source_ip = be32_to_cpu(match.mask->src);
acl_m->l3_dest_ip = be32_to_cpu(match.mask->dst);
}
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
struct flow_match_ports match;
flow_rule_match_ports(rule, &match);
acl_h->l4_source_port = be16_to_cpu(match.key->src);
acl_h->l4_dest_port = be16_to_cpu(match.key->dst);
acl_m->l4_source_port = be16_to_cpu(match.mask->src);
acl_m->l4_dest_port = be16_to_cpu(match.mask->dst);
}
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
struct flow_match_ip match;
flow_rule_match_ip(rule, &match);
if (match.mask->ttl != 0) {
NL_SET_ERR_MSG_MOD(extack,
"Matching on TTL not supported");
return -EOPNOTSUPP;
}
if ((match.mask->tos & 0x3) != 0) {
NL_SET_ERR_MSG_MOD(extack,
"Matching on ECN not supported, only DSCP");
return -EOPNOTSUPP;
}
acl_h->l3_dscp = match.key->tos >> 2;
acl_m->l3_dscp = match.mask->tos >> 2;
}
return 0;
}
Annotation
- Immediate include surface: `dpaa2-switch.h`.
- Detected declarations: `function dpaa2_switch_flower_parse_key`, `function dpaa2_switch_acl_entry_add`, `function dpaa2_switch_acl_entry_remove`, `function dpaa2_switch_acl_entry_add_to_list`, `function list_for_each_safe`, `function dpaa2_switch_acl_entry_get_by_index`, `function list_for_each_entry`, `function dpaa2_switch_acl_entry_set_precedence`, `function dpaa2_switch_acl_tbl_add_entry`, `function dpaa2_switch_acl_tbl_find_entry_by_cookie`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.