drivers/net/ethernet/freescale/dpaa2/dpsw.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/freescale/dpaa2/dpsw.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/freescale/dpaa2/dpsw.h- Extension
.h- Size
- 23837 bytes
- Lines
- 792
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct fsl_mc_iostruct dpsw_irq_cfgstruct dpsw_attrstruct dpsw_ctrl_if_attrstruct dpsw_ctrl_if_pools_cfgstruct dpsw_ctrl_if_dest_cfgstruct dpsw_ctrl_if_queue_cfgstruct dpsw_link_cfgstruct dpsw_link_statestruct dpsw_tci_cfgstruct dpsw_stp_cfgstruct dpsw_if_attrstruct dpsw_vlan_cfgstruct dpsw_vlan_if_cfgstruct dpsw_fdb_unicast_cfgstruct fdb_dump_entrystruct dpsw_fdb_multicast_cfgstruct dpsw_fdb_attrstruct dpsw_fdb_cfgstruct dpsw_egress_flood_cfgstruct dpsw_acl_cfgstruct dpsw_acl_if_cfgstruct dpsw_acl_fieldsstruct dpsw_acl_keystruct dpsw_acl_resultstruct dpsw_acl_entry_cfgstruct dpsw_reflection_cfgenum dpsw_component_typeenum dpsw_flooding_cfgenum dpsw_broadcast_cfgenum dpsw_queue_typeenum dpsw_ctrl_if_destenum dpsw_actionenum dpsw_stp_stateenum dpsw_accepted_framesenum dpsw_counterenum dpsw_fdb_entry_typeenum dpsw_learning_modeenum dpsw_flood_typeenum dpsw_acl_actionenum dpsw_reflection_filter
Annotated Snippet
struct dpsw_irq_cfg {
u64 addr;
u32 val;
int irq_num;
};
int dpsw_set_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u8 irq_index, u8 en);
int dpsw_set_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u8 irq_index, u32 mask);
int dpsw_get_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u8 irq_index, u32 *status);
int dpsw_clear_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
u8 irq_index, u32 status);
/**
* struct dpsw_attr - Structure representing DPSW attributes
* @id: DPSW object ID
* @options: Enable/Disable DPSW features
* @max_vlans: Maximum Number of VLANs
* @max_meters_per_if: Number of meters per interface
* @max_fdbs: Maximum Number of FDBs
* @max_fdb_entries: Number of FDB entries for default FDB table;
* 0 - indicates default 1024 entries.
* @fdb_aging_time: Default FDB aging time for default FDB table;
* 0 - indicates default 300 seconds
* @max_fdb_mc_groups: Number of multicast groups in each FDB table;
* 0 - indicates default 32
* @mem_size: DPSW frame storage memory size
* @num_ifs: Number of interfaces
* @num_vlans: Current number of VLANs
* @num_fdbs: Current number of FDBs
* @component_type: Component type of this bridge
* @flooding_cfg: Flooding configuration (PER_VLAN - default, PER_FDB)
* @broadcast_cfg: Broadcast configuration (PER_OBJECT - default, PER_FDB)
*/
struct dpsw_attr {
int id;
u64 options;
u16 max_vlans;
u8 max_meters_per_if;
u8 max_fdbs;
u16 max_fdb_entries;
u16 fdb_aging_time;
u16 max_fdb_mc_groups;
u16 num_ifs;
u16 mem_size;
u16 num_vlans;
u8 num_fdbs;
enum dpsw_component_type component_type;
enum dpsw_flooding_cfg flooding_cfg;
enum dpsw_broadcast_cfg broadcast_cfg;
};
int dpsw_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
struct dpsw_attr *attr);
/**
* struct dpsw_ctrl_if_attr - Control interface attributes
* @rx_fqid: Receive FQID
* @rx_err_fqid: Receive error FQID
* @tx_err_conf_fqid: Transmit error and confirmation FQID
*/
struct dpsw_ctrl_if_attr {
u32 rx_fqid;
u32 rx_err_fqid;
u32 tx_err_conf_fqid;
};
int dpsw_ctrl_if_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 token, struct dpsw_ctrl_if_attr *attr);
enum dpsw_queue_type {
DPSW_QUEUE_RX,
DPSW_QUEUE_TX_ERR_CONF,
DPSW_QUEUE_RX_ERR,
};
#define DPSW_MAX_DPBP 8
/**
* struct dpsw_ctrl_if_pools_cfg - Control interface buffer pools configuration
* @num_dpbp: Number of DPBPs
* @pools: Array of buffer pools parameters; The number of valid entries
* must match 'num_dpbp' value
* @pools.dpbp_id: DPBP object ID
* @pools.buffer_size: Buffer size
Annotation
- Detected declarations: `struct fsl_mc_io`, `struct dpsw_irq_cfg`, `struct dpsw_attr`, `struct dpsw_ctrl_if_attr`, `struct dpsw_ctrl_if_pools_cfg`, `struct dpsw_ctrl_if_dest_cfg`, `struct dpsw_ctrl_if_queue_cfg`, `struct dpsw_link_cfg`, `struct dpsw_link_state`, `struct dpsw_tci_cfg`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.