drivers/net/ethernet/freescale/enetc/enetc4_hw.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/freescale/enetc/enetc4_hw.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/freescale/enetc/enetc4_hw.h
Extension
.h
Size
15058 bytes
Lines
436
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ENETC4_HW_H_
#define __ENETC4_HW_H_

#define NXP_ENETC_VENDOR_ID		0x1131
#define NXP_ENETC_PF_DEV_ID		0xe101
#define NXP_ENETC_PPM_DEV_ID		0xe110

/**********************Station interface registers************************/
/* Station interface LSO segmentation flag mask register 0/1 */
#define ENETC4_SILSOSFMR0		0x1300
#define  SILSOSFMR0_TCP_MID_SEG		GENMASK(27, 16)
#define  SILSOSFMR0_TCP_1ST_SEG		GENMASK(11, 0)
#define  SILSOSFMR0_VAL_SET(first, mid)	(FIELD_PREP(SILSOSFMR0_TCP_MID_SEG, mid) | \
					 FIELD_PREP(SILSOSFMR0_TCP_1ST_SEG, first))

#define ENETC4_SILSOSFMR1		0x1304
#define  SILSOSFMR1_TCP_LAST_SEG	GENMASK(11, 0)
#define   ENETC4_TCP_FLAGS_FIN		BIT(0)
#define   ENETC4_TCP_FLAGS_SYN		BIT(1)
#define   ENETC4_TCP_FLAGS_RST		BIT(2)
#define   ENETC4_TCP_FLAGS_PSH		BIT(3)
#define   ENETC4_TCP_FLAGS_ACK		BIT(4)
#define   ENETC4_TCP_FLAGS_URG		BIT(5)
#define   ENETC4_TCP_FLAGS_ECE		BIT(6)
#define   ENETC4_TCP_FLAGS_CWR		BIT(7)
#define   ENETC4_TCP_FLAGS_NS		BIT(8)
/* According to tso_build_hdr(), clear all special flags for not last packet. */
#define ENETC4_TCP_NL_SEG_FLAGS_DMASK	(ENETC4_TCP_FLAGS_FIN | \
					 ENETC4_TCP_FLAGS_RST | ENETC4_TCP_FLAGS_PSH)

/***************************ENETC port registers**************************/
#define ENETC4_ECAPR0			0x0
#define  ECAPR0_RFS			BIT(2)
#define  ECAPR0_TSD			BIT(5)
#define  ECAPR0_RSS			BIT(8)
#define  ECAPR0_RSC			BIT(9)
#define  ECAPR0_LSO			BIT(10)
#define  ECAPR0_WO			BIT(13)

#define ENETC4_ECAPR1			0x4
#define  ECAPR1_NUM_TCS			GENMASK(6, 4)
#define  ECAPR1_NUM_MCH			GENMASK(9, 8)
#define  ECAPR1_NUM_UCH			GENMASK(11, 10)
#define  ECAPR1_NUM_MSIX		GENMASK(22, 12)
#define  ECAPR1_NUM_VSI			GENMASK(27, 24)
#define  ECAPR1_NUM_IPV			BIT(31)

#define ENETC4_ECAPR2			0x8
#define  ECAPR2_NUM_TX_BDR		GENMASK(9, 0)
#define  ECAPR2_NUM_RX_BDR		GENMASK(25, 16)

#define ENETC4_PMR			0x10
#define  PMR_SI_EN(a)			BIT((16 + (a)))

/* Port Pause ON/OFF threshold register */
#define ENETC4_PPAUONTR			0x108
#define ENETC4_PPAUOFFTR		0x10c

/* Port ingress congestion DRa (a=0,1,2,3) discard count register */
#define ENETC4_PICDRDCR(a)		((a) * 0x10 + 0x140)

/* Port Station interface promiscuous MAC mode register */
#define ENETC4_PSIPMMR			0x200
#define  PSIPMMR_SI_MAC_UP(a)		BIT(a) /* a = SI index */
#define  PSIPMMR_SI_MAC_MP(a)		BIT((a) + 16)

/* Port Station interface promiscuous VLAN mode register */
#define ENETC4_PSIPVMR			0x204

/* Port broadcast frames dropped due to MAC filtering register */
#define ENETC4_PBFDSIR			0x208

/* Port frame drop MAC source address pruning register */
#define ENETC4_PFDMSAPR			0x20c

/* Port RSS key register n. n = 0,1,2,...,9 */
#define ENETC4_PRSSKR(n)		((n) * 0x4 + 0x250)

/* Port station interface MAC address filtering capability register */
#define ENETC4_PSIMAFCAPR		0x280
#define  PSIMAFCAPR_NUM_MAC_AFTE	GENMASK(11, 0)

/* Port unicast frames dropped due to MAC filtering register */
#define ENETC4_PUFDMFR			0x284

/* Port multicast frames dropped due to MAC filtering register */
#define ENETC4_PMFDMFR			0x288

/* Port station interface VLAN filtering capability register */
#define ENETC4_PSIVLANFCAPR		0x2c0

Annotation

Implementation Notes