drivers/net/ethernet/freescale/gianfar.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/freescale/gianfar.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/freescale/gianfar.h
Extension
.h
Size
43505 bytes
Lines
1370
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ethtool_flow_spec_container {
	struct ethtool_rx_flow_spec fs;
	struct list_head list;
};

struct ethtool_rx_list {
	struct list_head list;
	unsigned int count;
};

/* Length for FCB */
#define GMAC_FCB_LEN 8

/* Length for TxPAL */
#define GMAC_TXPAL_LEN 16

/* Default padding amount */
#define DEFAULT_PADDING 2

/* Number of bytes to align the rx bufs to */
#define RXBUF_ALIGNMENT 64

#define DRV_NAME "gfar-enet"

/* MAXIMUM NUMBER OF QUEUES SUPPORTED */
#define MAX_TX_QS	0x8
#define MAX_RX_QS	0x8

/* MAXIMUM NUMBER OF GROUPS SUPPORTED */
#define MAXGROUPS 0x2

/* These need to be powers of 2 for this driver */
#define DEFAULT_TX_RING_SIZE	256
#define DEFAULT_RX_RING_SIZE	256

#define GFAR_RX_BUFF_ALLOC	16

#define GFAR_RX_MAX_RING_SIZE   256
#define GFAR_TX_MAX_RING_SIZE   256

#define FBTHR_SHIFT        24
#define DEFAULT_RX_LFC_THR  16
#define DEFAULT_LFC_PTVVAL  4

#define GFAR_RXB_TRUESIZE 2048
#define GFAR_SKBFRAG_OVR (RXBUF_ALIGNMENT \
			  + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
#define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
#define GFAR_SKBFRAG_SIZE (GFAR_RXB_SIZE + GFAR_SKBFRAG_OVR)

#define TX_RING_MOD_MASK(size) (size-1)
#define RX_RING_MOD_MASK(size) (size-1)
#define GFAR_JUMBO_FRAME_SIZE 9600

#define DEFAULT_FIFO_TX_THR 0x100
#define DEFAULT_FIFO_TX_STARVE 0x40
#define DEFAULT_FIFO_TX_STARVE_OFF 0x80

/* The number of Exact Match registers */
#define GFAR_EM_NUM	15

/* Latency of interface clock in nanoseconds */
/* Interface clock latency , in this case, means the
 * time described by a value of 1 in the interrupt
 * coalescing registers' time fields.  Since those fields
 * refer to the time it takes for 64 clocks to pass, the
 * latencies are as such:
 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
 */
#define GFAR_GBIT_TIME  512
#define GFAR_100_TIME   2560
#define GFAR_10_TIME    25600

#define DEFAULT_TX_COALESCE 1
#define DEFAULT_TXCOUNT	16
#define DEFAULT_TXTIME	21

#define DEFAULT_RXTIME	21

#define DEFAULT_RX_COALESCE 0
#define DEFAULT_RXCOUNT	0

/* TBI register addresses */
#define MII_TBICON		0x11

/* TBICON register bit fields */
#define TBICON_CLK_SELECT	0x0020

Annotation

Implementation Notes