drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c
Extension
.c
Size
18043 bytes
Lines
630
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (dsaf_mode) {
		case DSAF_MODE_ENABLE_FIX:
		case DSAF_MODE_DISABLE_FIX:
			qid_mode = PPE_QID_MODE0;
			hns_ppe_set_qid(ppe_common, 0);
			break;
		case DSAF_MODE_ENABLE_0VM:
		case DSAF_MODE_DISABLE_2PORT_64VM:
			qid_mode = PPE_QID_MODE3;
			break;
		case DSAF_MODE_ENABLE_8VM:
		case DSAF_MODE_DISABLE_2PORT_16VM:
			qid_mode = PPE_QID_MODE4;
			break;
		case DSAF_MODE_ENABLE_16VM:
		case DSAF_MODE_DISABLE_6PORT_0VM:
			qid_mode = PPE_QID_MODE5;
			break;
		case DSAF_MODE_ENABLE_32VM:
		case DSAF_MODE_DISABLE_6PORT_16VM:
			qid_mode = PPE_QID_MODE2;
			break;
		case DSAF_MODE_ENABLE_128VM:
		case DSAF_MODE_DISABLE_6PORT_4VM:
			qid_mode = PPE_QID_MODE1;
			break;
		case DSAF_MODE_DISABLE_2PORT_8VM:
			qid_mode = PPE_QID_MODE7;
			break;
		case DSAF_MODE_DISABLE_6PORT_2VM:
			qid_mode = PPE_QID_MODE6;
			break;
		default:
			dev_err(ppe_common->dev,
				"get ppe queue mode failed! dsaf_mode=%d\n",
				dsaf_mode);
			return -EINVAL;
		}
		hns_ppe_set_qid_mode(ppe_common, qid_mode);
	}

	dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG,
			 PPE_COMMON_CNT_CLR_CE_B, 1);

	return 0;
}

/*clr ppe exception irq*/
static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en)
{
	u32 clr_vlue = 0xfffffffful;
	u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/
	u32 vld_msk = 0;

	/*only care bit 0,1,7*/
	dsaf_set_bit(vld_msk, 0, 1);
	dsaf_set_bit(vld_msk, 1, 1);
	dsaf_set_bit(vld_msk, 7, 1);

	/*clr sts**/
	dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);

	/*for some reserved bits, so set 0**/
	dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
}

int hns_ppe_wait_tx_fifo_clean(struct hns_ppe_cb *ppe_cb)
{
	int wait_cnt;
	u32 val;

	wait_cnt = 0;
	while (wait_cnt++ < HNS_MAX_WAIT_CNT) {
		val = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG) & 0x3ffU;
		if (!val)
			break;

		usleep_range(100, 200);
	}

	if (wait_cnt >= HNS_MAX_WAIT_CNT) {
		dev_err(ppe_cb->dev, "hns ppe tx fifo clean wait timeout, still has %u pkt.\n",
			val);
		return -EBUSY;
	}

	return 0;
}

/**

Annotation

Implementation Notes