drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c- Extension
.c- Size
- 20438 bytes
- Lines
- 686
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
hnae3.hhclge_comm_cmd.h
Detected Declarations
function hclge_comm_cmd_config_regsfunction hclge_comm_cmd_init_regsfunction hclge_comm_cmd_reuse_descfunction hclge_comm_set_default_capabilityfunction hclge_comm_cmd_setup_basic_descfunction hclge_comm_firmware_compat_configfunction hclge_comm_free_cmd_descfunction hclge_comm_alloc_cmd_descfunction hclge_comm_build_api_capsfunction hclge_comm_capability_to_bitmapfunction hclge_comm_parse_capabilityfunction hclge_comm_alloc_cmd_queuefunction hclge_comm_cmd_query_version_and_capabilityfunction hclge_comm_is_special_opcodefunction hclge_comm_ring_spacefunction hclge_comm_cmd_copy_descfunction hclge_comm_is_valid_csq_clean_headfunction hclge_comm_cmd_csq_cleanfunction hclge_comm_cmd_csq_donefunction hclge_get_cmdq_tx_timeoutfunction hclge_comm_wait_for_respfunction hclge_comm_cmd_convert_err_codefunction hclge_comm_cmd_check_retvalfunction hclge_comm_cmd_check_resultfunction hclge_comm_cmd_sendfunction hclge_comm_cmd_uninit_regsfunction hclge_comm_cmd_uninitfunction hclge_comm_cmd_queue_initfunction hclge_comm_cmd_init_opsfunction hclge_comm_cmd_initexport hclge_comm_cmd_reuse_descexport hclge_comm_cmd_setup_basic_descexport hclge_comm_cmd_sendexport hclge_comm_cmd_uninitexport hclge_comm_cmd_queue_initexport hclge_comm_cmd_init_opsexport hclge_comm_cmd_init
Annotated Snippet
if (hclge_comm_cmd_csq_done(hw)) {
*is_completed = true;
break;
}
udelay(1);
timeout++;
} while (timeout < cmdq_tx_timeout);
}
static int hclge_comm_cmd_convert_err_code(u16 desc_ret)
{
struct hclge_comm_errcode hclge_comm_cmd_errcode[] = {
{ HCLGE_COMM_CMD_EXEC_SUCCESS, 0 },
{ HCLGE_COMM_CMD_NO_AUTH, -EPERM },
{ HCLGE_COMM_CMD_NOT_SUPPORTED, -EOPNOTSUPP },
{ HCLGE_COMM_CMD_QUEUE_FULL, -EXFULL },
{ HCLGE_COMM_CMD_NEXT_ERR, -ENOSR },
{ HCLGE_COMM_CMD_UNEXE_ERR, -ENOTBLK },
{ HCLGE_COMM_CMD_PARA_ERR, -EINVAL },
{ HCLGE_COMM_CMD_RESULT_ERR, -ERANGE },
{ HCLGE_COMM_CMD_TIMEOUT, -ETIME },
{ HCLGE_COMM_CMD_HILINK_ERR, -ENOLINK },
{ HCLGE_COMM_CMD_QUEUE_ILLEGAL, -ENXIO },
{ HCLGE_COMM_CMD_INVALID, -EBADR },
};
u32 errcode_count = ARRAY_SIZE(hclge_comm_cmd_errcode);
u32 i;
for (i = 0; i < errcode_count; i++)
if (hclge_comm_cmd_errcode[i].imp_errcode == desc_ret)
return hclge_comm_cmd_errcode[i].common_errno;
return -EIO;
}
static int hclge_comm_cmd_check_retval(struct hclge_comm_hw *hw,
struct hclge_desc *desc, int num,
int ntc)
{
u16 opcode, desc_ret;
int handle;
opcode = le16_to_cpu(desc[0].opcode);
for (handle = 0; handle < num; handle++) {
desc[handle] = hw->cmq.csq.desc[ntc];
ntc++;
if (ntc >= hw->cmq.csq.desc_num)
ntc = 0;
}
if (likely(!hclge_comm_is_special_opcode(opcode)))
desc_ret = le16_to_cpu(desc[num - 1].retval);
else
desc_ret = le16_to_cpu(desc[0].retval);
hw->cmq.last_status = desc_ret;
return hclge_comm_cmd_convert_err_code(desc_ret);
}
static int hclge_comm_cmd_check_result(struct hclge_comm_hw *hw,
struct hclge_desc *desc,
int num, int ntc)
{
bool is_completed = false;
int handle, ret;
/* If the command is sync, wait for the firmware to write back,
* if multi descriptors to be sent, use the first one to check
*/
if (HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag)))
hclge_comm_wait_for_resp(hw, le16_to_cpu(desc->opcode),
&is_completed);
if (!is_completed)
ret = -EBADE;
else
ret = hclge_comm_cmd_check_retval(hw, desc, num, ntc);
/* Clean the command send queue */
handle = hclge_comm_cmd_csq_clean(hw);
if (handle < 0)
ret = handle;
else if (handle != num)
dev_warn(&hw->cmq.csq.pdev->dev,
"cleaned %d, need to clean %d\n", handle, num);
return ret;
}
/**
* hclge_comm_cmd_send - send command to command queue
Annotation
- Immediate include surface: `hnae3.h`, `hclge_comm_cmd.h`.
- Detected declarations: `function hclge_comm_cmd_config_regs`, `function hclge_comm_cmd_init_regs`, `function hclge_comm_cmd_reuse_desc`, `function hclge_comm_set_default_capability`, `function hclge_comm_cmd_setup_basic_desc`, `function hclge_comm_firmware_compat_config`, `function hclge_comm_free_cmd_desc`, `function hclge_comm_alloc_cmd_desc`, `function hclge_comm_build_api_caps`, `function hclge_comm_capability_to_bitmap`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.