drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
Extension
.h
Size
20020 bytes
Lines
896
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hclge_misc_vector {
	u8 __iomem *addr;
	int vector_irq;
	char name[HNAE3_INT_NAME_LEN];
};

#define hclge_cmd_setup_basic_desc(desc, opcode, is_read) \
	hclge_comm_cmd_setup_basic_desc(desc, opcode, is_read)

#define HCLGE_TQP_REG_OFFSET		0x80000
#define HCLGE_TQP_REG_SIZE		0x200

#define HCLGE_FD_COUNTER_MAX_SIZE_DEV_V2	128
#define HCLGE_TQP_MAX_SIZE_DEV_V2	1024
#define HCLGE_TQP_EXT_REG_OFFSET	0x100

#define HCLGE_RCB_INIT_QUERY_TIMEOUT	10
#define HCLGE_RCB_INIT_FLAG_EN_B	0
#define HCLGE_RCB_INIT_FLAG_FINI_B	8
struct hclge_config_rcb_init_cmd {
	__le16 rcb_init_flag;
	u8 rsv[22];
};

struct hclge_tqp_map_cmd {
	__le16 tqp_id;	/* Absolute tqp id for in this pf */
	u8 tqp_vf;	/* VF id */
#define HCLGE_TQP_MAP_TYPE_PF		0
#define HCLGE_TQP_MAP_TYPE_VF		1
#define HCLGE_TQP_MAP_TYPE_B		0
#define HCLGE_TQP_MAP_EN_B		1
	u8 tqp_flag;	/* Indicate it's pf or vf tqp */
	__le16 tqp_vid; /* Virtual id in this pf/vf */
	u8 rsv[18];
};

#define HCLGE_VECTOR_ELEMENTS_PER_CMD	10

enum hclge_int_type {
	HCLGE_INT_TX,
	HCLGE_INT_RX,
	HCLGE_INT_EVENT,
};

struct hclge_ctrl_vector_chain_cmd {
#define HCLGE_VECTOR_ID_L_S	0
#define HCLGE_VECTOR_ID_L_M	GENMASK(7, 0)
	u8 int_vector_id_l;
	u8 int_cause_num;
#define HCLGE_INT_TYPE_S	0
#define HCLGE_INT_TYPE_M	GENMASK(1, 0)
#define HCLGE_TQP_ID_S		2
#define HCLGE_TQP_ID_M		GENMASK(12, 2)
#define HCLGE_INT_GL_IDX_S	13
#define HCLGE_INT_GL_IDX_M	GENMASK(14, 13)
	__le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
	u8 vfid;
#define HCLGE_VECTOR_ID_H_S	8
#define HCLGE_VECTOR_ID_H_M	GENMASK(15, 8)
	u8 int_vector_id_h;
};

#define HCLGE_MAX_TC_NUM		8
#define HCLGE_TC0_PRI_BUF_EN_B	15 /* Bit 15 indicate enable or not */
#define HCLGE_BUF_UNIT_S	7  /* Buf size is united by 128 bytes */
struct hclge_tx_buff_alloc_cmd {
	__le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
	u8 tx_buff_rsv[8];
};

struct hclge_rx_priv_buff_cmd {
	__le16 buf_num[HCLGE_MAX_TC_NUM];
	__le16 shared_buf;
	u8 rsv[6];
};

#define HCLGE_RX_PRIV_EN_B	15
#define HCLGE_TC_NUM_ONE_DESC	4
struct hclge_priv_wl {
	__le16 high;
	__le16 low;
};

struct hclge_rx_priv_wl_buf {
	struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
};

struct hclge_rx_com_thrd {
	struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
};

Annotation

Implementation Notes