drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c- Extension
.c- Size
- 15908 bytes
- Lines
- 683
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
hclge_main.hhclge_dcb.hhclge_tm.hhnae3.h
Detected Declarations
function hclge_ieee_ets_to_tm_infofunction hclge_tm_info_to_ieee_etsfunction hclge_ieee_getetsfunction hclge_dcb_common_validatefunction hclge_ets_tc_changedfunction hclge_ets_sch_mode_validatefunction hclge_ets_validatefunction hclge_map_updatefunction hclge_notify_down_uinitfunction hclge_notify_init_upfunction hclge_ieee_setetsfunction hclge_ieee_getpfcfunction hclge_ieee_setpfcfunction hclge_ieee_setappfunction hclge_ieee_delappfunction hclge_getdcbxfunction hclge_setdcbxfunction hclge_mqprio_qopt_checkfunction hclge_sync_mqprio_qoptfunction hclge_config_tcfunction hclge_setup_tcfunction hclge_dcb_ops_set
Annotated Snippet
switch (ets->tc_tsa[i]) {
case IEEE_8021QAZ_TSA_STRICT:
hdev->tm_info.tc_info[i].tc_sch_mode =
HCLGE_SCH_MODE_SP;
hdev->tm_info.pg_info[0].tc_dwrr[i] = 0;
break;
case IEEE_8021QAZ_TSA_ETS:
hdev->tm_info.tc_info[i].tc_sch_mode =
HCLGE_SCH_MODE_DWRR;
hdev->tm_info.pg_info[0].tc_dwrr[i] =
ets->tc_tx_bw[i];
break;
default:
/* Hardware only supports SP (strict priority)
* or ETS (enhanced transmission selection)
* algorithms, if we receive some other value
* from dcbnl, then throw an error.
*/
return -EINVAL;
}
}
hclge_tm_prio_tc_info_update(hdev, ets->prio_tc);
return 0;
}
static void hclge_tm_info_to_ieee_ets(struct hclge_dev *hdev,
struct ieee_ets *ets)
{
u32 i;
memset(ets, 0, sizeof(*ets));
ets->willing = 1;
ets->ets_cap = hdev->tc_max;
for (i = 0; i < HNAE3_MAX_TC; i++) {
ets->prio_tc[i] = hdev->tm_info.prio_tc[i];
if (i < hdev->tm_info.num_tc)
ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i];
else
ets->tc_tx_bw[i] = 0;
if (hdev->tm_info.tc_info[i].tc_sch_mode ==
HCLGE_SCH_MODE_SP)
ets->tc_tsa[i] = IEEE_8021QAZ_TSA_STRICT;
else
ets->tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
}
}
/* IEEE std */
static int hclge_ieee_getets(struct hnae3_handle *h, struct ieee_ets *ets)
{
struct hclge_vport *vport = hclge_get_vport(h);
struct hclge_dev *hdev = vport->back;
hclge_tm_info_to_ieee_ets(hdev, ets);
return 0;
}
static int hclge_dcb_common_validate(struct hclge_dev *hdev, u8 num_tc,
u8 *prio_tc)
{
int i;
if (num_tc > hdev->tc_max) {
dev_err(&hdev->pdev->dev,
"tc num checking failed, %u > tc_max(%u)\n",
num_tc, hdev->tc_max);
return -EINVAL;
}
for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
if (prio_tc[i] >= num_tc) {
dev_err(&hdev->pdev->dev,
"prio_tc[%d] checking failed, %u >= num_tc(%u)\n",
i, prio_tc[i], num_tc);
return -EINVAL;
}
}
if (num_tc > hdev->vport[0].alloc_tqps) {
dev_err(&hdev->pdev->dev,
"allocated tqp checking failed, %u > tqp(%u)\n",
num_tc, hdev->vport[0].alloc_tqps);
return -EINVAL;
}
Annotation
- Immediate include surface: `hclge_main.h`, `hclge_dcb.h`, `hclge_tm.h`, `hnae3.h`.
- Detected declarations: `function hclge_ieee_ets_to_tm_info`, `function hclge_tm_info_to_ieee_ets`, `function hclge_ieee_getets`, `function hclge_dcb_common_validate`, `function hclge_ets_tc_changed`, `function hclge_ets_sch_mode_validate`, `function hclge_ets_validate`, `function hclge_map_update`, `function hclge_notify_down_uinit`, `function hclge_notify_init_up`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.