drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
Extension
.c
Size
86330 bytes
Lines
3112
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (cmd == reg_info->cmd) {
			if (cmd == HNAE3_DBG_CMD_REG_TQP)
				return hclge_dbg_dump_reg_tqp(hdev,
							      reg_info, s);

			ret = hclge_dbg_dump_reg_common(hdev, reg_info, s);
			if (ret)
				break;
		}
	}

	return ret;
}

static int hclge_dbg_dump_bios_reg_cmd(struct seq_file *s, void *data)
{
	return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_BIOS_COMMON, s);
}

static int hclge_dbg_dump_ssu_reg_cmd(struct seq_file *s, void *data)
{
	return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_SSU, s);
}

static int hclge_dbg_dump_igu_egu_reg_cmd(struct seq_file *s, void *data)
{
	return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_IGU_EGU, s);
}

static int hclge_dbg_dump_rpu_reg_cmd(struct seq_file *s, void *data)
{
	return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_RPU, s);
}

static int hclge_dbg_dump_ncsi_reg_cmd(struct seq_file *s, void *data)
{
	return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_NCSI, s);
}

static int hclge_dbg_dump_rtc_reg_cmd(struct seq_file *s, void *data)
{
	return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_RTC, s);
}

static int hclge_dbg_dump_ppp_reg_cmd(struct seq_file *s, void *data)
{
	return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_PPP, s);
}

static int hclge_dbg_dump_rcb_reg_cmd(struct seq_file *s, void *data)
{
	return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_RCB, s);
}

static int hclge_dbg_dump_tqp_reg_cmd(struct seq_file *s, void *data)
{
	return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_TQP, s);
}

static int hclge_dbg_dump_tc(struct seq_file *s, void *data)
{
	struct hclge_dev *hdev = hclge_seq_file_to_hdev(s);
	struct hclge_ets_tc_weight_cmd *ets_weight;
	const char *sch_mode_str;
	struct hclge_desc desc;
	int ret;
	u8 i;

	if (!hnae3_dev_dcb_supported(hdev)) {
		dev_err(&hdev->pdev->dev,
			"Only DCB-supported dev supports tc\n");
		return -EOPNOTSUPP;
	}

	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, true);
	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
	if (ret) {
		dev_err(&hdev->pdev->dev, "failed to get tc weight, ret = %d\n",
			ret);
		return ret;
	}

	ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data;

	seq_printf(s, "enabled tc number: %u\n", hdev->tm_info.num_tc);
	seq_printf(s, "weight_offset: %u\n", ets_weight->weight_offset);

	seq_puts(s, "TC    MODE  WEIGHT\n");
	for (i = 0; i < HNAE3_MAX_TC; i++) {
		sch_mode_str = ets_weight->tc_weight[i] ? "dwrr" : "sp";

Annotation

Implementation Notes