drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
Extension
.h
Size
8808 bytes
Lines
270
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hclge_hw_blk {
	u32 msk;
	const char *name;
	int (*config_err_int)(struct hclge_dev *hdev, bool en);
};

struct hclge_hw_error {
	u32 int_msk;
	const char *msg;
	enum hnae3_reset_type reset_level;
};

struct hclge_hw_module_id {
	enum hclge_mod_name_list module_id;
	const char *msg;
	void (*query_reg_info)(struct hclge_dev *hdev);
};

struct hclge_hw_type_id {
	enum hclge_err_type_list type_id;
	const char *msg;
	bool cause_by_vf; /* indicate the error may from vf exception */
};

struct hclge_sum_err_info {
	u8 reset_type;
	u8 mod_num;
	u8 rsv[2];
};

struct hclge_mod_err_info {
	u8 mod_id;
	u8 err_num;
	u8 rsv[2];
};

struct hclge_type_reg_err_info {
	u8 type_id;
	u8 reg_num;
	u8 rsv[2];
	u32 hclge_reg[HCLGE_REG_NUM_MAX];
};

struct hclge_mod_reg_info {
	const char *reg_name;
	bool has_suffix; /* add suffix for register name */
	/* the positions of reg values in hclge_desc.data */
	u8 reg_offset_group[HCLGE_MOD_REG_GROUP_MAX_SIZE];
	u8 group_size;
};

/* This structure defines cmdq used to query the hardware module debug
 * regisgers.
 */
struct hclge_mod_reg_common_msg {
	enum hclge_opcode_type cmd;
	struct hclge_desc *desc;
	u8 bd_num; /* the bd number of hclge_desc used */
	bool need_para; /* whether this cmdq needs to add para */

	/* the regs need to print */
	const struct hclge_mod_reg_info *result_regs;
	u16 result_regs_size;
};

int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);
int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state);
int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en);
void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev);
bool hclge_find_error_source(struct hclge_dev *hdev);
void hclge_handle_occurred_error(struct hclge_dev *hdev);
pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
			       unsigned long *reset_requests);
int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev);
int hclge_handle_mac_tnl(struct hclge_dev *hdev);
int hclge_handle_vf_queue_err_ras(struct hclge_dev *hdev);
#endif

Annotation

Implementation Notes