drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
Extension
.h
Size
7277 bytes
Lines
282
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hclge_pg_to_pri_link_cmd {
	u8 pg_id;
	u8 rsvd1[3];
	u8 pri_bit_map;
};

struct hclge_qs_to_pri_link_cmd {
	__le16 qs_id;
	__le16 rsvd;
	u8 priority;
#define HCLGE_TM_QS_PRI_LINK_VLD_MSK	BIT(0)
	u8 link_vld;
};

struct hclge_nq_to_qs_link_cmd {
	__le16 nq_id;
	__le16 rsvd;
#define HCLGE_TM_Q_QS_LINK_VLD_MSK	BIT(10)
#define HCLGE_TM_QS_ID_L_MSK		GENMASK(9, 0)
#define HCLGE_TM_QS_ID_L_S		0
#define HCLGE_TM_QS_ID_H_MSK		GENMASK(14, 10)
#define HCLGE_TM_QS_ID_H_S		10
#define HCLGE_TM_QS_ID_H_EXT_S		11
#define HCLGE_TM_QS_ID_H_EXT_MSK	GENMASK(15, 11)
	__le16 qset_id;
};

struct hclge_tqp_tx_queue_tc_cmd {
	__le16 queue_id;
	__le16 rsvd;
	u8 tc_id;
	u8 rev[3];
};

struct hclge_pg_weight_cmd {
	u8 pg_id;
	u8 dwrr;
};

struct hclge_priority_weight_cmd {
	u8 pri_id;
	u8 dwrr;
};

struct hclge_pri_sch_mode_cfg_cmd {
	u8 pri_id;
	u8 rsvd[3];
	u8 sch_mode;
};

struct hclge_qs_sch_mode_cfg_cmd {
	__le16 qs_id;
	u8 rsvd[2];
	u8 sch_mode;
};

struct hclge_qs_weight_cmd {
	__le16 qs_id;
	u8 dwrr;
};

struct hclge_ets_tc_weight_cmd {
	u8 tc_weight[HNAE3_MAX_TC];
	u8 weight_offset;
	u8 rsvd[15];
};

#define HCLGE_TM_SHAP_IR_B_MSK  GENMASK(7, 0)
#define HCLGE_TM_SHAP_IR_B_LSH	0
#define HCLGE_TM_SHAP_IR_U_MSK  GENMASK(11, 8)
#define HCLGE_TM_SHAP_IR_U_LSH	8
#define HCLGE_TM_SHAP_IR_S_MSK  GENMASK(15, 12)
#define HCLGE_TM_SHAP_IR_S_LSH	12
#define HCLGE_TM_SHAP_BS_B_MSK  GENMASK(20, 16)
#define HCLGE_TM_SHAP_BS_B_LSH	16
#define HCLGE_TM_SHAP_BS_S_MSK  GENMASK(25, 21)
#define HCLGE_TM_SHAP_BS_S_LSH	21

enum hclge_shap_bucket {
	HCLGE_TM_SHAP_C_BUCKET = 0,
	HCLGE_TM_SHAP_P_BUCKET,
};

/* set bit HCLGE_TM_RATE_VLD to 1 means use 'rate' to config shaping */
#define HCLGE_TM_RATE_VLD	0

struct hclge_pri_shapping_cmd {
	u8 pri_id;
	u8 rsvd[3];
	__le32 pri_shapping_para;

Annotation

Implementation Notes