drivers/net/ethernet/huawei/hinic/hinic_hw_csr.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/huawei/hinic/hinic_hw_csr.h

File Facts

System: Linux kernel
Corpus path: drivers/net/ethernet/huawei/hinic/hinic_hw_csr.h
Extension: .h
Size: 5323 bytes
Lines: 140
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef HINIC_HW_CSR_H
#define HINIC_HW_CSR_H

/* HW interface registers */
#define HINIC_CSR_FUNC_ATTR0_ADDR                       0x0
#define HINIC_CSR_FUNC_ATTR1_ADDR                       0x4
#define HINIC_CSR_FUNC_ATTR2_ADDR			0x8
#define HINIC_CSR_FUNC_ATTR4_ADDR                       0x10
#define HINIC_CSR_FUNC_ATTR5_ADDR                       0x14

#define HINIC_DMA_ATTR_BASE                             0xC80
#define HINIC_ELECTION_BASE                             0x4200

#define HINIC_DMA_ATTR_STRIDE                           0x4
#define HINIC_CSR_DMA_ATTR_ADDR(idx)                    \
	(HINIC_DMA_ATTR_BASE + (idx) * HINIC_DMA_ATTR_STRIDE)

#define HINIC_PPF_ELECTION_STRIDE                       0x4

#define HINIC_CSR_PPF_ELECTION_ADDR(idx)                \
	(HINIC_ELECTION_BASE +  (idx) * HINIC_PPF_ELECTION_STRIDE)

/* API CMD registers */
#define HINIC_CSR_API_CMD_BASE                          0xF000

#define HINIC_CSR_API_CMD_STRIDE                        0x100

#define HINIC_CSR_API_CMD_CHAIN_HEAD_HI_ADDR(idx)       \
	(HINIC_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC_CSR_API_CMD_STRIDE)

#define HINIC_CSR_API_CMD_CHAIN_HEAD_LO_ADDR(idx)       \
	(HINIC_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC_CSR_API_CMD_STRIDE)

#define HINIC_CSR_API_CMD_STATUS_HI_ADDR(idx)           \
	(HINIC_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC_CSR_API_CMD_STRIDE)

#define HINIC_CSR_API_CMD_STATUS_LO_ADDR(idx)           \
	(HINIC_CSR_API_CMD_BASE + 0xC + (idx) * HINIC_CSR_API_CMD_STRIDE)

#define HINIC_CSR_API_CMD_CHAIN_NUM_CELLS_ADDR(idx)     \
	(HINIC_CSR_API_CMD_BASE + 0x10 + (idx) * HINIC_CSR_API_CMD_STRIDE)

#define HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR(idx)          \
	(HINIC_CSR_API_CMD_BASE + 0x14 + (idx) * HINIC_CSR_API_CMD_STRIDE)

#define HINIC_CSR_API_CMD_CHAIN_PI_ADDR(idx)            \
	(HINIC_CSR_API_CMD_BASE + 0x1C + (idx) * HINIC_CSR_API_CMD_STRIDE)

#define HINIC_CSR_API_CMD_CHAIN_REQ_ADDR(idx)           \
	(HINIC_CSR_API_CMD_BASE + 0x20 + (idx) * HINIC_CSR_API_CMD_STRIDE)

#define HINIC_CSR_API_CMD_STATUS_ADDR(idx)              \
	(HINIC_CSR_API_CMD_BASE + 0x30 + (idx) * HINIC_CSR_API_CMD_STRIDE)

/* MSI-X registers */
#define HINIC_CSR_MSIX_CTRL_BASE                        0x2000
#define HINIC_CSR_MSIX_CNT_BASE                         0x2004

#define HINIC_CSR_MSIX_STRIDE                           0x8

#define HINIC_CSR_MSIX_CTRL_ADDR(idx)                   \
	(HINIC_CSR_MSIX_CTRL_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)

#define HINIC_CSR_MSIX_CNT_ADDR(idx)                    \
	(HINIC_CSR_MSIX_CNT_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)

/* EQ registers */
#define HINIC_AEQ_MTT_OFF_BASE_ADDR                     0x200
#define HINIC_CEQ_MTT_OFF_BASE_ADDR                     0x400

#define HINIC_EQ_MTT_OFF_STRIDE                         0x40

#define HINIC_CSR_AEQ_MTT_OFF(id)                       \
	(HINIC_AEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)

#define HINIC_CSR_CEQ_MTT_OFF(id)                       \
	(HINIC_CEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)

#define HINIC_CSR_EQ_PAGE_OFF_STRIDE                    8

#define HINIC_CSR_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num)    \
	(HINIC_CSR_AEQ_MTT_OFF(q_id) + \
	 (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)

#define HINIC_CSR_CEQ_HI_PHYS_ADDR_REG(q_id, pg_num)    \
	(HINIC_CSR_CEQ_MTT_OFF(q_id) +          \
	 (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)

#define HINIC_CSR_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num)    \
	(HINIC_CSR_AEQ_MTT_OFF(q_id) + \

Annotation

Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.