drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h

File Facts

System: Linux kernel
Corpus path: drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h
Extension: .h
Size: 12861 bytes
Lines: 661
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/pci.h
linux/types.h
linux/bitops.h
net/devlink.h
hinic_hw_if.h
hinic_hw_eqs.h
hinic_hw_mgmt.h
hinic_hw_qp.h
hinic_hw_io.h
hinic_hw_mbox.h

Detected Declarations

struct hinic_cap
struct hinic_cmd_fw_ctxt
struct hinic_cmd_hw_ioctxt
struct hinic_cmd_io_status
struct hinic_cmd_clear_io_res
struct hinic_cmd_set_res_state
struct hinic_ceq_ctrl_reg
struct hinic_cmd_base_qpn
struct hinic_cmd_hw_ci
struct hinic_cmd_l2nic_reset
struct hinic_msix_config
struct hinic_set_random_id
struct hinic_board_info
struct hinic_comm_board_info
struct hinic_hwdev
struct hinic_nic_cb
struct comm_mgmt_self_msg_sub_info
struct comm_mgmt_self_msg_info
struct hinic_pfhwdev
struct hinic_dev_cap
struct hinic_fault_event
struct hinic_cmd_fault_event
struct hinic_mgmt_watchdog_info
enum hw_ioctxt_set_cmdq_depth
enum hinic_port_cmd
enum hinic_hilink_cmd
enum hinic_ucode_cmd
enum hinic_mgmt_msg_cmd
enum hinic_cb_state
enum hinic_res_state
enum hinic_fault_type
enum hinic_fault_err_level

Annotated Snippet

struct hinic_cap {
	u16     max_qps;
	u16     num_qps;
	u8		max_vf;
	u16     max_vf_qps;
};

enum hw_ioctxt_set_cmdq_depth {
	HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT,
	HW_IOCTXT_SET_CMDQ_DEPTH_ENABLE,
};

enum hinic_port_cmd {
	HINIC_PORT_CMD_VF_REGISTER = 0x0,
	HINIC_PORT_CMD_VF_UNREGISTER = 0x1,

	HINIC_PORT_CMD_CHANGE_MTU = 0x2,

	HINIC_PORT_CMD_ADD_VLAN = 0x3,
	HINIC_PORT_CMD_DEL_VLAN = 0x4,

	HINIC_PORT_CMD_SET_ETS = 0x7,
	HINIC_PORT_CMD_GET_ETS = 0x8,

	HINIC_PORT_CMD_SET_PFC = 0x5,

	HINIC_PORT_CMD_SET_MAC = 0x9,
	HINIC_PORT_CMD_GET_MAC = 0xA,
	HINIC_PORT_CMD_DEL_MAC = 0xB,

	HINIC_PORT_CMD_SET_RX_MODE = 0xC,

	HINIC_PORT_CMD_SET_ANTI_ATTACK_RATE = 0xD,

	HINIC_PORT_CMD_GET_PAUSE_INFO = 0x14,
	HINIC_PORT_CMD_SET_PAUSE_INFO = 0x15,

	HINIC_PORT_CMD_GET_LINK_STATE = 0x18,

	HINIC_PORT_CMD_SET_LRO = 0x19,

	HINIC_PORT_CMD_SET_RX_CSUM = 0x1A,

	HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 0x1B,

	HINIC_PORT_CMD_GET_PORT_STATISTICS = 0x1C,

	HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 0x1D,

	HINIC_PORT_CMD_GET_VPORT_STAT = 0x1E,

	HINIC_PORT_CMD_CLEAN_VPORT_STAT	= 0x1F,

	HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 0x25,

	HINIC_PORT_CMD_SET_PORT_STATE = 0x29,
	HINIC_PORT_CMD_GET_PORT_STATE = 0x30,

	HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 0x2B,

	HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 0x2C,

	HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 0x2D,

	HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 0x2E,

	HINIC_PORT_CMD_GET_RSS_CTX_TBL = 0x2F,

	HINIC_PORT_CMD_SET_RSS_CTX_TBL = 0x30,

	HINIC_PORT_CMD_RSS_TEMP_MGR	= 0x31,

	HINIC_PORT_CMD_RD_LINE_TBL = 0x39,

	HINIC_PORT_CMD_RSS_CFG = 0x42,

	HINIC_PORT_CMD_GET_PHY_TYPE = 0x44,

	HINIC_PORT_CMD_FWCTXT_INIT = 0x45,

	HINIC_PORT_CMD_GET_LOOPBACK_MODE = 0x48,
	HINIC_PORT_CMD_SET_LOOPBACK_MODE = 0x49,

	HINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE = 0x4A,
	HINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE = 0x4B,

	HINIC_PORT_CMD_ENABLE_SPOOFCHK = 0x4E,

	HINIC_PORT_CMD_GET_MGMT_VERSION = 0x58,

Annotation

Immediate include surface: `linux/pci.h`, `linux/types.h`, `linux/bitops.h`, `net/devlink.h`, `hinic_hw_if.h`, `hinic_hw_eqs.h`, `hinic_hw_mgmt.h`, `hinic_hw_qp.h`.
Detected declarations: `struct hinic_cap`, `struct hinic_cmd_fw_ctxt`, `struct hinic_cmd_hw_ioctxt`, `struct hinic_cmd_io_status`, `struct hinic_cmd_clear_io_res`, `struct hinic_cmd_set_res_state`, `struct hinic_ceq_ctrl_reg`, `struct hinic_cmd_base_qpn`, `struct hinic_cmd_hw_ci`, `struct hinic_cmd_l2nic_reset`.
Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.