drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c- Extension
.c- Size
- 28288 bytes
- Lines
- 1081
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/delay.hlinux/dma-mapping.hhinic3_cmdq.hhinic3_eqs.hhinic3_hwdev.hhinic3_hwif.hhinic3_mbox.h
Detected Declarations
enum cmdq_data_formatenum cmdq_scmd_typeenum cmdq_ctrl_sect_lenenum cmdq_bufdesc_lenenum cmdq_completion_formatenum cmdq_cmd_typefunction hinic3_dump_cmdq_wqe_headfunction hinic3_free_cmd_buffunction cmdq_clear_cmd_buffunction clear_wqe_complete_bitfunction cmdq_arm_ceq_handlerfunction cmdq_update_cmd_statusfunction cmdq_sync_cmd_handlerfunction hinic3_cmdq_ceq_handlerfunction cmdq_params_validfunction wait_cmdqs_enablefunction cmdq_set_completionfunction cmdq_set_lcmd_bufdescfunction cmdq_set_dbfunction cmdq_wqe_fillfunction cmdq_prepare_wqe_ctrlfunction cmdq_set_lcmd_wqefunction hinic3_cmdq_sync_timeout_checkfunction clear_cmd_infofunction wait_cmdq_sync_cmd_completionfunction cmdq_sync_cmd_execfunction cmdq_sync_cmd_direct_respfunction cmdq_sync_cmd_detail_respfunction hinic3_cmd_buf_pair_initfunction hinic3_cmd_buf_pair_uninitfunction hinic3_cmdq_direct_respfunction hinic3_cmdq_detail_respfunction cmdq_init_queue_ctxtfunction init_cmdqfunction hinic3_set_cmdq_ctxtfunction hinic3_set_cmdq_ctxtsfunction create_cmdq_wqfunction destroy_cmdq_wqfunction init_cmdqsfunction cmdq_flush_sync_cmdfunction hinic3_cmdq_flush_cmdfunction hinic3_cmdq_flush_sync_cmdfunction hinic3_cmdq_reset_all_cmd_buffunction hinic3_reinit_cmdq_ctxtsfunction hinic3_cmdqs_initfunction hinic3_cmdqs_freefunction hinic3_cmdq_idle
Annotated Snippet
switch (cmd_info->cmd_type) {
case HINIC3_CMD_TYPE_NONE:
return;
case HINIC3_CMD_TYPE_TIMEOUT:
dev_warn(hwdev->dev, "Cmdq timeout, q_id: %u, ci: %u\n",
cmdq_type, ci);
hinic3_dump_cmdq_wqe_head(hwdev, wqe);
fallthrough;
case HINIC3_CMD_TYPE_FAKE_TIMEOUT:
cmdq_clear_cmd_buf(cmd_info, hwdev);
clear_wqe_complete_bit(cmdq, wqe, ci);
break;
case HINIC3_CMD_TYPE_SET_ARM:
/* arm_bit was set until here */
if (cmdq_arm_ceq_handler(cmdq, wqe, ci))
return;
break;
default:
/* only arm bit is using scmd wqe,
* the other wqe is lcmd
*/
wqe_lcmd = &wqe->wqe_lcmd;
ctrl_info = wqe_lcmd->ctrl.ctrl_info;
if (!CMDQ_WQE_COMPLETED(ctrl_info))
return;
dma_rmb();
/* For FORCE_STOP cmd_type, we also need to wait for
* the firmware processing to complete to prevent the
* firmware from accessing the released cmd_buf
*/
if (cmd_info->cmd_type == HINIC3_CMD_TYPE_FORCE_STOP) {
cmdq_clear_cmd_buf(cmd_info, hwdev);
clear_wqe_complete_bit(cmdq, wqe, ci);
} else {
cmdq_sync_cmd_handler(cmdq, wqe, ci);
}
break;
}
}
}
static int cmdq_params_valid(const struct hinic3_hwdev *hwdev,
const struct hinic3_cmd_buf *buf_in)
{
if (le16_to_cpu(buf_in->size) > CMDQ_BUF_SIZE) {
dev_err(hwdev->dev, "Invalid CMDQ buffer size: 0x%x\n",
le16_to_cpu(buf_in->size));
return -EINVAL;
}
return 0;
}
static int wait_cmdqs_enable(struct hinic3_cmdqs *cmdqs)
{
unsigned long end;
end = jiffies + msecs_to_jiffies(CMDQ_ENABLE_WAIT_TIMEOUT);
do {
if (cmdqs->status & HINIC3_CMDQ_ENABLE)
return 0;
usleep_range(1000, 2000);
} while (time_before(jiffies, end) && !cmdqs->disable_flag &&
cmdqs->hwdev->chip_present_flag);
cmdqs->disable_flag = 1;
return -EBUSY;
}
static void cmdq_set_completion(struct cmdq_completion *complete,
struct hinic3_cmd_buf *buf_out)
{
struct hinic3_sge *sge = &complete->resp.sge;
hinic3_set_sge(sge, buf_out->dma_addr, cpu_to_le32(CMDQ_BUF_SIZE));
}
static struct cmdq_wqe *cmdq_get_wqe(struct hinic3_wq *wq, u16 *pi)
{
if (!hinic3_wq_free_wqebbs(wq))
return NULL;
return hinic3_wq_get_one_wqebb(wq, pi);
}
static void cmdq_set_lcmd_bufdesc(struct cmdq_wqe_lcmd *wqe,
struct hinic3_cmd_buf *buf_in)
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/delay.h`, `linux/dma-mapping.h`, `hinic3_cmdq.h`, `hinic3_eqs.h`, `hinic3_hwdev.h`, `hinic3_hwif.h`, `hinic3_mbox.h`.
- Detected declarations: `enum cmdq_data_format`, `enum cmdq_scmd_type`, `enum cmdq_ctrl_sect_len`, `enum cmdq_bufdesc_len`, `enum cmdq_completion_format`, `enum cmdq_cmd_type`, `function hinic3_dump_cmdq_wqe_head`, `function hinic3_free_cmd_buf`, `function cmdq_clear_cmd_buf`, `function clear_wqe_complete_bit`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.