drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c- Extension
.c- Size
- 21917 bytes
- Lines
- 841
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hhinic3_csr.hhinic3_eqs.hhinic3_hwdev.hhinic3_hwif.hhinic3_mbox.h
Detected Declarations
function HINIC3_AEQ_HI_PHYS_ADDR_REGfunction hinic3_aeq_register_cbfunction hinic3_aeq_unregister_cbfunction hinic3_ceq_register_cbfunction hinic3_ceq_unregister_cbfunction set_eq_cons_idxfunction ceq_event_handlerfunction aeq_event_handlerfunction aeq_irq_handlerfunction ceq_irq_handlerfunction reschedule_aeq_handlerfunction eq_irq_handlerfunction aeq_irq_workfunction aeq_interruptfunction ceq_interruptfunction hinic3_set_ceq_ctrl_regfunction set_eq_ctrlsfunction ceq_elements_initfunction aeq_elements_initfunction eq_elements_initfunction alloc_eq_pagesfunction eq_calc_page_size_and_numfunction request_eq_irqfunction reset_eqfunction init_eqfunction remove_eqfunction hinic3_aeqs_initfunction hinic3_aeqs_freefunction hinic3_dump_aeq_infofunction hinic3_ceqs_initfunction hinic3_ceqs_freefunction hinic3_dump_ceq_info
Annotated Snippet
if (eq->cons_idx == eq->eq_len) {
eq->cons_idx = 0;
eq->wrapped = !eq->wrapped;
}
if (++eqe_cnt >= HINIC3_EQ_UPDATE_CI_STEP) {
eqe_cnt = 0;
set_eq_cons_idx(eq, HINIC3_EQ_NOT_ARMED);
}
}
return -EAGAIN;
}
static int ceq_irq_handler(struct hinic3_eq *eq)
{
struct hinic3_ceqs *ceqs;
u32 eqe_cnt = 0;
__be32 ceqe_raw;
__le32 ceqe;
u32 i;
ceqs = ceq_to_ceqs(eq);
for (i = 0; i < HINIC3_TASK_PROCESS_EQE_LIMIT; i++) {
ceqe_raw = *get_curr_ceq_elem(eq);
ceqe = (__force __le32)swab32((__force __u32)ceqe_raw);
/* HW updates wrapped bit, when it adds eq element event */
if (EQ_ELEM_DESC_GET(ceqe, WRAPPED) == eq->wrapped)
return 0;
ceq_event_handler(ceqs, ceqe);
eq->cons_idx++;
if (eq->cons_idx == eq->eq_len) {
eq->cons_idx = 0;
eq->wrapped = !eq->wrapped;
}
if (++eqe_cnt >= HINIC3_EQ_UPDATE_CI_STEP) {
eqe_cnt = 0;
set_eq_cons_idx(eq, HINIC3_EQ_NOT_ARMED);
}
}
return -EAGAIN;
}
static void reschedule_aeq_handler(struct hinic3_eq *eq)
{
struct hinic3_aeqs *aeqs = aeq_to_aeqs(eq);
queue_work(aeqs->workq, &eq->aeq_work);
}
static int eq_irq_handler(struct hinic3_eq *eq)
{
int err;
if (eq->type == HINIC3_AEQ)
err = aeq_irq_handler(eq);
else
err = ceq_irq_handler(eq);
set_eq_cons_idx(eq, err ? HINIC3_EQ_NOT_ARMED :
HINIC3_EQ_ARMED);
return err;
}
static void aeq_irq_work(struct work_struct *work)
{
struct hinic3_eq *eq = container_of(work, struct hinic3_eq, aeq_work);
int err;
err = eq_irq_handler(eq);
if (err)
reschedule_aeq_handler(eq);
}
static irqreturn_t aeq_interrupt(int irq, void *data)
{
struct workqueue_struct *workq;
struct hinic3_eq *aeq = data;
struct hinic3_hwdev *hwdev;
struct hinic3_aeqs *aeqs;
aeqs = aeq_to_aeqs(aeq);
hwdev = aeq->hwdev;
/* clear resend timer cnt register */
Annotation
- Immediate include surface: `linux/delay.h`, `hinic3_csr.h`, `hinic3_eqs.h`, `hinic3_hwdev.h`, `hinic3_hwif.h`, `hinic3_mbox.h`.
- Detected declarations: `function HINIC3_AEQ_HI_PHYS_ADDR_REG`, `function hinic3_aeq_register_cb`, `function hinic3_aeq_unregister_cb`, `function hinic3_ceq_register_cb`, `function hinic3_ceq_unregister_cb`, `function set_eq_cons_idx`, `function ceq_event_handler`, `function aeq_event_handler`, `function aeq_irq_handler`, `function ceq_irq_handler`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.