drivers/net/ethernet/huawei/hinic3/hinic3_eqs.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/huawei/hinic3/hinic3_eqs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/huawei/hinic3/hinic3_eqs.h- Extension
.h- Size
- 3458 bytes
- Lines
- 128
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/interrupt.hhinic3_hw_cfg.hhinic3_queue_common.h
Detected Declarations
struct hinic3_eqstruct hinic3_aeq_elemstruct hinic3_aeqsstruct hinic3_ceqsenum hinic3_eq_typeenum hinic3_eq_intr_modeenum hinic3_eq_ci_arm_stateenum hinic3_aeq_typeenum hinic3_ceq_event
Annotated Snippet
struct hinic3_eq {
struct hinic3_hwdev *hwdev;
struct hinic3_queue_pages qpages;
u16 q_id;
enum hinic3_eq_type type;
u32 eq_len;
u32 cons_idx;
u8 wrapped;
u32 irq_id;
u16 msix_entry_idx;
char irq_name[HINIC3_EQ_IRQ_NAME_LEN];
struct work_struct aeq_work;
u64 soft_intr_jif;
};
struct hinic3_aeq_elem {
u8 aeqe_data[HINIC3_AEQE_DATA_SIZE];
__be32 desc;
};
enum hinic3_aeq_type {
HINIC3_HW_INTER_INT = 0,
HINIC3_MBX_FROM_FUNC = 1,
HINIC3_MSG_FROM_FW = 2,
HINIC3_MAX_AEQ_EVENTS = 6,
};
typedef void (*hinic3_aeq_event_cb)(struct hinic3_hwdev *hwdev, u8 *data,
u8 size);
struct hinic3_aeqs {
struct hinic3_hwdev *hwdev;
hinic3_aeq_event_cb aeq_cb[HINIC3_MAX_AEQ_EVENTS];
struct hinic3_eq aeq[HINIC3_MAX_AEQS];
u16 num_aeqs;
struct workqueue_struct *workq;
/* lock for aeq event flag */
spinlock_t aeq_lock;
};
enum hinic3_ceq_event {
HINIC3_CMDQ = 3,
HINIC3_MAX_CEQ_EVENTS = 6,
};
typedef void (*hinic3_ceq_event_cb)(struct hinic3_hwdev *hwdev,
__le32 ceqe_data);
struct hinic3_ceqs {
struct hinic3_hwdev *hwdev;
hinic3_ceq_event_cb ceq_cb[HINIC3_MAX_CEQ_EVENTS];
struct hinic3_eq ceq[HINIC3_MAX_CEQS];
u16 num_ceqs;
/* lock for ceq event flag */
spinlock_t ceq_lock;
};
int hinic3_aeqs_init(struct hinic3_hwdev *hwdev, u16 num_aeqs,
struct msix_entry *msix_entries);
void hinic3_aeqs_free(struct hinic3_hwdev *hwdev);
int hinic3_aeq_register_cb(struct hinic3_hwdev *hwdev,
enum hinic3_aeq_type event,
hinic3_aeq_event_cb hwe_cb);
void hinic3_aeq_unregister_cb(struct hinic3_hwdev *hwdev,
enum hinic3_aeq_type event);
void hinic3_dump_aeq_info(struct hinic3_hwdev *hwdev);
int hinic3_ceqs_init(struct hinic3_hwdev *hwdev, u16 num_ceqs,
struct msix_entry *msix_entries);
void hinic3_ceqs_free(struct hinic3_hwdev *hwdev);
int hinic3_ceq_register_cb(struct hinic3_hwdev *hwdev,
enum hinic3_ceq_event event,
hinic3_ceq_event_cb callback);
void hinic3_ceq_unregister_cb(struct hinic3_hwdev *hwdev,
enum hinic3_ceq_event event);
void hinic3_dump_ceq_info(struct hinic3_hwdev *hwdev);
#endif
Annotation
- Immediate include surface: `linux/interrupt.h`, `hinic3_hw_cfg.h`, `hinic3_queue_common.h`.
- Detected declarations: `struct hinic3_eq`, `struct hinic3_aeq_elem`, `struct hinic3_aeqs`, `struct hinic3_ceqs`, `enum hinic3_eq_type`, `enum hinic3_eq_intr_mode`, `enum hinic3_eq_ci_arm_state`, `enum hinic3_aeq_type`, `enum hinic3_ceq_event`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.