drivers/net/ethernet/huawei/hinic3/hinic3_hw_intf.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/huawei/hinic3/hinic3_hw_intf.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/huawei/hinic3/hinic3_hw_intf.h- Extension
.h- Size
- 7729 bytes
- Lines
- 301
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bits.hlinux/types.h
Detected Declarations
struct mgmt_msg_headstruct mgmt_msg_paramsstruct cfg_cmd_dev_capstruct comm_cmd_cfg_msix_ctrl_regstruct comm_cmd_func_resetstruct comm_cmd_feature_negostruct comm_global_attrstruct comm_cmd_get_glb_attrstruct comm_cmd_set_func_svc_used_statestruct comm_cmd_set_dma_attrstruct comm_cmd_set_ceq_ctrl_regstruct comm_cmd_cfg_wq_page_sizestruct comm_cmd_set_root_ctxtstruct comm_cmdq_ctxt_infostruct comm_cmd_set_cmdq_ctxtstruct comm_cmd_clear_resourcestruct comm_cmd_sync_timestruct comm_cmd_bdf_infostruct comm_cmd_get_fw_versionenum mgmt_mod_typeenum cfg_cmdenum comm_cmdenum comm_func_reset_bitsenum comm_func_svc_typeenum hinic3_service_typefunction mgmt_msg_params_init_default
Annotated Snippet
struct mgmt_msg_head {
u8 status;
u8 version;
u8 rsvd0[6];
};
struct mgmt_msg_params {
const void *buf_in;
u32 in_size;
void *buf_out;
u32 expected_out_size;
u32 timeout_ms;
};
/* CMDQ MODULE_TYPE */
enum mgmt_mod_type {
/* HW communication module */
MGMT_MOD_COMM = 0,
/* L2NIC module */
MGMT_MOD_L2NIC = 1,
/* Configuration module */
MGMT_MOD_CFGM = 7,
MGMT_MOD_HILINK = 14,
/* hardware max module id */
MGMT_MOD_HW_MAX = 20,
};
static inline void mgmt_msg_params_init_default(struct mgmt_msg_params *msg_params,
void *inout_buf, u32 buf_size)
{
msg_params->buf_in = inout_buf;
msg_params->buf_out = inout_buf;
msg_params->in_size = buf_size;
msg_params->expected_out_size = buf_size;
msg_params->timeout_ms = 0;
}
enum cfg_cmd {
CFG_CMD_GET_DEV_CAP = 0,
};
/* Device capabilities, defined by hw */
struct cfg_cmd_dev_cap {
struct mgmt_msg_head head;
u16 func_id;
u16 rsvd1;
/* Public resources */
u8 host_id;
u8 ep_id;
u8 er_id;
u8 port_id;
u16 host_total_func;
u8 host_pf_num;
u8 pf_id_start;
u16 host_vf_num;
u16 vf_id_start;
u8 host_oq_id_mask_val;
u8 timer_en;
u8 host_valid_bitmap;
u8 rsvd_host;
u16 svc_cap_en;
u16 max_vf;
u8 flexq_en;
u8 valid_cos_bitmap;
u8 port_cos_valid_bitmap;
u8 rsvd2[45];
/* l2nic */
u16 nic_max_sq_id;
u16 nic_max_rq_id;
u16 nic_default_num_queues;
u8 rsvd3[250];
};
/* COMM Commands between Driver to fw */
enum comm_cmd {
/* Commands for clearing FLR and resources */
COMM_CMD_FUNC_RESET = 0,
COMM_CMD_FEATURE_NEGO = 1,
COMM_CMD_FLUSH_DOORBELL = 2,
COMM_CMD_START_FLUSH = 3,
COMM_CMD_GET_GLOBAL_ATTR = 5,
COMM_CMD_SET_FUNC_SVC_USED_STATE = 7,
/* Driver Configuration Commands */
Annotation
- Immediate include surface: `linux/bits.h`, `linux/types.h`.
- Detected declarations: `struct mgmt_msg_head`, `struct mgmt_msg_params`, `struct cfg_cmd_dev_cap`, `struct comm_cmd_cfg_msix_ctrl_reg`, `struct comm_cmd_func_reset`, `struct comm_cmd_feature_nego`, `struct comm_global_attr`, `struct comm_cmd_get_glb_attr`, `struct comm_cmd_set_func_svc_used_state`, `struct comm_cmd_set_dma_attr`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.