drivers/net/ethernet/huawei/hinic3/hinic3_hwdev.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/huawei/hinic3/hinic3_hwdev.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/huawei/hinic3/hinic3_hwdev.c- Extension
.c- Size
- 16392 bytes
- Lines
- 658
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
hinic3_cmdq.hhinic3_csr.hhinic3_eqs.hhinic3_hw_comm.hhinic3_hwdev.hhinic3_hwif.hhinic3_mbox.hhinic3_mgmt.h
Detected Declarations
enum hinic3_hwdev_init_statefunction hinic3_comm_aeqs_initfunction hinic3_comm_ceqs_initfunction hinic3_comm_mbox_initfunction hinic3_comm_mbox_freefunction init_aeqs_msix_attrfunction init_ceqs_msix_attrfunction hinic3_comm_pf_to_mgmt_initfunction hinic3_comm_pf_to_mgmt_freefunction init_basic_mgmt_channelfunction free_base_mgmt_channelfunction dma_attr_table_initfunction init_basic_attributesfunction hinic3_comm_cmdqs_initfunction hinic3_comm_cmdqs_freefunction init_cmdqs_channelfunction hinic3_free_cmdqs_channelfunction hinic3_init_comm_chfunction hinic3_uninit_comm_chfunction hinic3_auto_sync_time_workfunction hinic3_init_ppf_workfunction hinic3_free_ppf_workfunction hinic3_adev_idx_allocfunction hinic3_adev_idx_freefunction hinic3_init_hwdevfunction hinic3_free_hwdevfunction hinic3_set_api_stopfunction test_bit
Annotated Snippet
if (err) {
dev_err(hwdev->dev, "Set msix attr for aeq %d failed\n",
q_id);
return err;
}
}
return 0;
}
static int init_ceqs_msix_attr(struct hinic3_hwdev *hwdev)
{
struct hinic3_ceqs *ceqs = hwdev->ceqs;
struct hinic3_interrupt_info info = {};
struct hinic3_eq *eq;
u16 q_id;
int err;
info.interrupt_coalesc_set = 1;
info.pending_limit = HINIC3_DEFAULT_EQ_MSIX_PENDING_LIMIT;
info.coalesc_timer_cfg = HINIC3_DEFAULT_EQ_MSIX_COALESC_TIMER_CFG;
info.resend_timer_cfg = HINIC3_DEFAULT_EQ_MSIX_RESEND_TIMER_CFG;
for (q_id = 0; q_id < ceqs->num_ceqs; q_id++) {
eq = &ceqs->ceq[q_id];
info.msix_index = eq->msix_entry_idx;
err = hinic3_set_interrupt_cfg(hwdev, info);
if (err) {
dev_err(hwdev->dev, "Set msix attr for ceq %u failed\n",
q_id);
return err;
}
}
return 0;
}
static int hinic3_comm_pf_to_mgmt_init(struct hinic3_hwdev *hwdev)
{
int err;
if (HINIC3_IS_VF(hwdev))
return 0;
err = hinic3_pf_to_mgmt_init(hwdev);
if (err)
return err;
set_bit(HINIC3_HWDEV_MGMT_INITED, &hwdev->func_state);
return 0;
}
static void hinic3_comm_pf_to_mgmt_free(struct hinic3_hwdev *hwdev)
{
if (HINIC3_IS_VF(hwdev))
return;
spin_lock_bh(&hwdev->channel_lock);
clear_bit(HINIC3_HWDEV_MGMT_INITED, &hwdev->func_state);
spin_unlock_bh(&hwdev->channel_lock);
hinic3_aeq_unregister_cb(hwdev, HINIC3_MSG_FROM_FW);
hinic3_pf_to_mgmt_free(hwdev);
}
static int init_basic_mgmt_channel(struct hinic3_hwdev *hwdev)
{
int err;
err = hinic3_comm_aeqs_init(hwdev);
if (err) {
dev_err(hwdev->dev, "Failed to init async event queues\n");
return err;
}
err = hinic3_comm_mbox_init(hwdev);
if (err) {
dev_err(hwdev->dev, "Failed to init mailbox\n");
goto err_free_comm_aeqs;
}
err = init_aeqs_msix_attr(hwdev);
if (err) {
dev_err(hwdev->dev, "Failed to init aeqs msix attr\n");
goto err_free_comm_mbox;
}
return 0;
Annotation
- Immediate include surface: `hinic3_cmdq.h`, `hinic3_csr.h`, `hinic3_eqs.h`, `hinic3_hw_comm.h`, `hinic3_hwdev.h`, `hinic3_hwif.h`, `hinic3_mbox.h`, `hinic3_mgmt.h`.
- Detected declarations: `enum hinic3_hwdev_init_state`, `function hinic3_comm_aeqs_init`, `function hinic3_comm_ceqs_init`, `function hinic3_comm_mbox_init`, `function hinic3_comm_mbox_free`, `function init_aeqs_msix_attr`, `function init_ceqs_msix_attr`, `function hinic3_comm_pf_to_mgmt_init`, `function hinic3_comm_pf_to_mgmt_free`, `function init_basic_mgmt_channel`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.