drivers/net/ethernet/huawei/hinic3/hinic3_irq.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/huawei/hinic3/hinic3_irq.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/huawei/hinic3/hinic3_irq.c
Extension
.c
Size
7937 bytes
Lines
292
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (err) {
			netdev_err(netdev, "Failed to request Rx irq\n");
			goto err_release_irqs;
		}

		INIT_WORK(&irq_cfg->rxq->dim.work, hinic3_rx_dim_work);
		irq_cfg->rxq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;

		netif_queue_set_napi(irq_cfg->netdev, q_id,
				     NETDEV_QUEUE_TYPE_RX, &irq_cfg->napi);
		netif_queue_set_napi(irq_cfg->netdev, q_id,
				     NETDEV_QUEUE_TYPE_TX, &irq_cfg->napi);

		hinic3_set_msix_auto_mask_state(nic_dev->hwdev,
						irq_cfg->msix_entry_idx,
						HINIC3_SET_MSIX_AUTO_MASK);
		hinic3_set_msix_state(nic_dev->hwdev, irq_cfg->msix_entry_idx,
				      HINIC3_MSIX_ENABLE);
	}

	return 0;

err_release_irqs:
	while (q_id > 0) {
		q_id--;
		irq_cfg = &nic_dev->q_params.irq_cfg[q_id];
		qp_del_napi(irq_cfg);
		netif_queue_set_napi(irq_cfg->netdev, q_id,
				     NETDEV_QUEUE_TYPE_RX, NULL);
		netif_queue_set_napi(irq_cfg->netdev, q_id,
				     NETDEV_QUEUE_TYPE_TX, NULL);

		hinic3_set_msix_state(nic_dev->hwdev, irq_cfg->msix_entry_idx,
				      HINIC3_MSIX_DISABLE);
		hinic3_set_msix_auto_mask_state(nic_dev->hwdev,
						irq_cfg->msix_entry_idx,
						HINIC3_CLR_MSIX_AUTO_MASK);
		hinic3_release_irq(irq_cfg);
		disable_work_sync(&irq_cfg->rxq->dim.work);
	}

	return err;
}

void hinic3_qps_irq_uninit(struct net_device *netdev)
{
	struct hinic3_nic_dev *nic_dev = netdev_priv(netdev);
	struct hinic3_irq_cfg *irq_cfg;
	u16 q_id;

	for (q_id = 0; q_id < nic_dev->q_params.num_qps; q_id++) {
		irq_cfg = &nic_dev->q_params.irq_cfg[q_id];
		qp_del_napi(irq_cfg);
		netif_queue_set_napi(irq_cfg->netdev, q_id,
				     NETDEV_QUEUE_TYPE_RX, NULL);
		netif_queue_set_napi(irq_cfg->netdev, q_id,
				     NETDEV_QUEUE_TYPE_TX, NULL);
		hinic3_set_msix_state(nic_dev->hwdev, irq_cfg->msix_entry_idx,
				      HINIC3_MSIX_DISABLE);
		hinic3_set_msix_auto_mask_state(nic_dev->hwdev,
						irq_cfg->msix_entry_idx,
						HINIC3_CLR_MSIX_AUTO_MASK);
		hinic3_release_irq(irq_cfg);
		disable_work_sync(&irq_cfg->rxq->dim.work);
	}
}

Annotation

Implementation Notes