drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c- Extension
.c- Size
- 25357 bytes
- Lines
- 929
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/dma-mapping.hhinic3_common.hhinic3_csr.hhinic3_eqs.hhinic3_hwdev.hhinic3_hwif.hhinic3_mbox.h
Detected Declarations
function resp_mbox_handlerfunction mbox_segment_validfunction recv_mbox_handlerfunction hinic3_mbox_func_aeqe_handlerfunction init_mbox_dma_queuefunction uninit_mbox_dma_queuefunction hinic3_init_mbox_dma_queuefunction hinic3_uninit_mbox_dma_queuefunction alloc_mbox_msg_channelfunction free_mbox_msg_channelfunction init_mgmt_msg_channelfunction uninit_mgmt_msg_channelfunction hinic3_init_func_mbox_msg_channelfunction hinic3_uninit_func_mbox_msg_channelfunction prepare_send_mboxfunction alloc_mbox_wb_statusfunction free_mbox_wb_statusfunction hinic3_mbox_pre_initfunction hinic3_init_mboxfunction hinic3_free_mboxfunction mbox_dma_msg_xorfunction is_msg_queue_fullfunction mbox_prepare_dma_entryfunction mbox_prepare_dma_msgfunction clear_mbox_statusfunction mbox_dword_writefunction mbox_copy_headerfunction mbox_copy_send_datafunction write_mbox_msg_attrfunction hinic3_dump_mbox_regfunction get_mbox_statusfunction check_mbox_wb_statusfunction send_mbox_segfunction send_mbox_msgfunction set_mbox_to_func_eventfunction check_mbox_msg_finishfunction wait_mbox_msg_completionfunction hinic3_send_mbox_to_mgmtfunction hinic3_response_mbox_to_mgmtfunction hinic3_send_mbox_to_mgmt_no_ack
Annotated Snippet
if (left <= MBOX_SEG_LEN) {
header &= cpu_to_le64(~MBOX_MSG_HEADER_SEG_LEN_MASK);
header |=
cpu_to_le64(MBOX_MSG_HEADER_SET(left, SEG_LEN) |
MBOX_MSG_HEADER_SET(1, LAST));
seg_len = left;
}
err = send_mbox_seg(mbox, header, dst_func, msg_seg,
seg_len, msg_info);
if (err) {
dev_err(hwdev->dev, "Failed to send mbox seg, seq_id=0x%llx\n",
MBOX_MSG_HEADER_GET(header, SEQID));
goto err_send;
}
left -= MBOX_SEG_LEN;
msg_seg += MBOX_SEG_LEN;
seq_id++;
header &= cpu_to_le64(~MBOX_MSG_HEADER_SEG_LEN_MASK);
header |= cpu_to_le64(MBOX_MSG_HEADER_SET(seq_id, SEQID));
}
err_send:
mutex_unlock(&mbox->mbox_seg_send_lock);
return err;
}
static void set_mbox_to_func_event(struct hinic3_mbox *mbox,
enum mbox_event_state event_flag)
{
spin_lock(&mbox->mbox_lock);
mbox->event_flag = event_flag;
spin_unlock(&mbox->mbox_lock);
}
static enum hinic3_wait_return check_mbox_msg_finish(void *priv_data)
{
struct hinic3_mbox *mbox = priv_data;
if (!mbox->hwdev->chip_present_flag)
return HINIC3_WAIT_PROCESS_ERR;
return (mbox->event_flag == MBOX_EVENT_SUCCESS) ?
HINIC3_WAIT_PROCESS_CPL : HINIC3_WAIT_PROCESS_WAITING;
}
static int wait_mbox_msg_completion(struct hinic3_mbox *mbox,
u32 timeout)
{
u32 wait_time;
int err;
wait_time = (timeout != 0) ? timeout : MBOX_COMP_POLLING_TIMEOUT_MS;
err = hinic3_wait_for_timeout(mbox, check_mbox_msg_finish,
wait_time, USEC_PER_MSEC);
if (err) {
set_mbox_to_func_event(mbox, MBOX_EVENT_TIMEOUT);
return err;
}
set_mbox_to_func_event(mbox, MBOX_EVENT_END);
return 0;
}
int hinic3_send_mbox_to_mgmt(struct hinic3_hwdev *hwdev, u8 mod, u16 cmd,
const struct mgmt_msg_params *msg_params)
{
struct hinic3_mbox *mbox = hwdev->mbox;
struct mbox_msg_info msg_info = {};
struct hinic3_msg_desc *msg_desc;
u32 msg_len;
int err;
if (!hwdev->chip_present_flag)
return -EPERM;
/* expect response message */
msg_desc = get_mbox_msg_desc(mbox, MBOX_MSG_RESP, MBOX_MGMT_FUNC_ID);
mutex_lock(&mbox->mbox_send_lock);
msg_info.msg_id = (mbox->send_msg_id + 1) & 0xF;
mbox->send_msg_id = msg_info.msg_id;
set_mbox_to_func_event(mbox, MBOX_EVENT_START);
err = send_mbox_msg(mbox, mod, cmd, msg_params->buf_in,
msg_params->in_size, MBOX_MGMT_FUNC_ID,
MBOX_MSG_SEND, MBOX_MSG_ACK, &msg_info);
if (err) {
dev_err(hwdev->dev, "Send mailbox mod %u, cmd %u failed, msg_id: %u, err: %d\n",
Annotation
- Immediate include surface: `linux/dma-mapping.h`, `hinic3_common.h`, `hinic3_csr.h`, `hinic3_eqs.h`, `hinic3_hwdev.h`, `hinic3_hwif.h`, `hinic3_mbox.h`.
- Detected declarations: `function resp_mbox_handler`, `function mbox_segment_valid`, `function recv_mbox_handler`, `function hinic3_mbox_func_aeqe_handler`, `function init_mbox_dma_queue`, `function uninit_mbox_dma_queue`, `function hinic3_init_mbox_dma_queue`, `function hinic3_uninit_mbox_dma_queue`, `function alloc_mbox_msg_channel`, `function free_mbox_msg_channel`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.