drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h- Extension
.h- Size
- 4220 bytes
- Lines
- 148
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/mutex.h
Detected Declarations
struct hinic3_hwdevstruct mgmt_msg_paramsstruct mbox_msg_infostruct hinic3_msg_descstruct hinic3_msg_channelstruct hinic3_send_mboxstruct mbox_dma_msgstruct mbox_dma_queuestruct hinic3_mboxenum mbox_msg_direction_typeenum mbox_msg_ack_typeenum mbox_msg_data_typeenum mbox_msg_src_typeenum mbox_msg_aeq_typeenum mbox_event_state
Annotated Snippet
struct mbox_msg_info {
u8 msg_id;
u8 status;
};
struct hinic3_msg_desc {
u8 *msg;
__le16 msg_len;
u8 seq_id;
u8 mod;
__le16 cmd;
struct mbox_msg_info msg_info;
};
struct hinic3_msg_channel {
struct hinic3_msg_desc resp_msg;
struct hinic3_msg_desc recv_msg;
};
struct hinic3_send_mbox {
u8 __iomem *data;
void *wb_vaddr;
dma_addr_t wb_paddr;
};
enum mbox_event_state {
MBOX_EVENT_START = 0,
MBOX_EVENT_FAIL = 1,
MBOX_EVENT_SUCCESS = 2,
MBOX_EVENT_TIMEOUT = 3,
MBOX_EVENT_END = 4,
};
struct mbox_dma_msg {
__le32 xor;
__le32 dma_addr_high;
__le32 dma_addr_low;
__le32 msg_len;
__le64 rsvd;
};
struct mbox_dma_queue {
void *dma_buf_vaddr;
dma_addr_t dma_buf_paddr;
u16 depth;
u16 prod_idx;
u16 cons_idx;
};
struct hinic3_mbox {
struct hinic3_hwdev *hwdev;
/* lock for send mbox message and ack message */
struct mutex mbox_send_lock;
/* lock for send message transmission.
* The lock hierarchy is mbox_send_lock -> mbox_seg_send_lock.
*/
struct mutex mbox_seg_send_lock;
struct hinic3_send_mbox send_mbox;
struct mbox_dma_queue sync_msg_queue;
struct mbox_dma_queue async_msg_queue;
struct workqueue_struct *workq;
/* driver and MGMT CPU */
struct hinic3_msg_channel mgmt_msg;
/* VF to PF */
struct hinic3_msg_channel *func_msg;
u8 send_msg_id;
enum mbox_event_state event_flag;
/* lock for mbox event flag */
spinlock_t mbox_lock;
};
void hinic3_mbox_func_aeqe_handler(struct hinic3_hwdev *hwdev, u8 *header,
u8 size);
int hinic3_init_mbox(struct hinic3_hwdev *hwdev);
void hinic3_free_mbox(struct hinic3_hwdev *hwdev);
int hinic3_send_mbox_to_mgmt(struct hinic3_hwdev *hwdev, u8 mod, u16 cmd,
const struct mgmt_msg_params *msg_params);
void hinic3_response_mbox_to_mgmt(struct hinic3_hwdev *hwdev, u8 mod, u16 cmd,
const void *buf_in, u32 in_size, u16 msg_id);
int hinic3_send_mbox_to_mgmt_no_ack(struct hinic3_hwdev *hwdev, u8 mod, u16 cmd,
const struct mgmt_msg_params *msg_params);
#endif
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/mutex.h`.
- Detected declarations: `struct hinic3_hwdev`, `struct mgmt_msg_params`, `struct mbox_msg_info`, `struct hinic3_msg_desc`, `struct hinic3_msg_channel`, `struct hinic3_send_mbox`, `struct mbox_dma_msg`, `struct mbox_dma_queue`, `struct hinic3_mbox`, `enum mbox_msg_direction_type`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.