drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.h
Extension
.h
Size
4043 bytes
Lines
146
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hinic3_io_queue {
	struct hinic3_wq  wq;
	u8                owner;
	u16               q_id;
	u16               msix_entry_idx;
	u8 __iomem        *db_addr;
	u16               *cons_idx_addr;
} ____cacheline_aligned;

static inline u16 hinic3_get_sq_local_ci(const struct hinic3_io_queue *sq)
{
	const struct hinic3_wq *wq = &sq->wq;

	return wq->cons_idx & wq->idx_mask;
}

static inline u16 hinic3_get_sq_local_pi(const struct hinic3_io_queue *sq)
{
	const struct hinic3_wq *wq = &sq->wq;

	return wq->prod_idx & wq->idx_mask;
}

static inline u16 hinic3_get_sq_hw_ci(const struct hinic3_io_queue *sq)
{
	const struct hinic3_wq *wq = &sq->wq;

	return READ_ONCE(*sq->cons_idx_addr) & wq->idx_mask;
}

/* ******************** DB INFO ******************** */
#define DB_INFO_QID_MASK    GENMASK(12, 0)
#define DB_INFO_CFLAG_MASK  BIT(23)
#define DB_INFO_COS_MASK    GENMASK(26, 24)
#define DB_INFO_TYPE_MASK   GENMASK(31, 27)
#define DB_INFO_SET(val, member)  \
	FIELD_PREP(DB_INFO_##member##_MASK, val)

#define DB_PI_LOW_MASK   0xFFU
#define DB_PI_HIGH_MASK  0xFFU
#define DB_PI_HI_SHIFT   8
#define DB_PI_LOW(pi)    ((pi) & DB_PI_LOW_MASK)
#define DB_PI_HIGH(pi)   (((pi) >> DB_PI_HI_SHIFT) & DB_PI_HIGH_MASK)
#define DB_ADDR(q, pi)   ((u64 __iomem *)((q)->db_addr) + DB_PI_LOW(pi))
#define DB_SRC_TYPE      1

/* CFLAG_DATA_PATH */
#define DB_CFLAG_DP_SQ   0
#define DB_CFLAG_DP_RQ   1

struct hinic3_nic_db {
	__le32 db_info;
	__le32 pi_hi;
};

static inline void hinic3_write_db(struct hinic3_io_queue *queue, int cos,
				   u8 cflag, u16 pi)
{
	struct hinic3_nic_db db;

	db.db_info =
		cpu_to_le32(DB_INFO_SET(DB_SRC_TYPE, TYPE) |
			    DB_INFO_SET(cflag, CFLAG) |
			    DB_INFO_SET(cos, COS) |
			    DB_INFO_SET(queue->q_id, QID));
	db.pi_hi = cpu_to_le32(DB_PI_HIGH(pi));

	writeq(*((u64 *)&db), DB_ADDR(queue, pi));
}

struct hinic3_dyna_qp_params {
	u16                    num_qps;
	u32                    sq_depth;
	u32                    rq_depth;

	struct hinic3_io_queue *sqs;
	struct hinic3_io_queue *rqs;
};

struct hinic3_nic_io {
	struct hinic3_io_queue *sq;
	struct hinic3_io_queue *rq;

	u16                    num_qps;
	u16                    max_qps;

	/* Base address for consumer index of all tx queues. Each queue is
	 * given a full cache line to hold its consumer index. HW updates
	 * current consumer index as it consumes tx WQEs.
	 */

Annotation

Implementation Notes