drivers/net/ethernet/huawei/hinic3/hinic3_queue_common.c

File Facts

System

Linux kernel

Corpus path

drivers/net/ethernet/huawei/hinic3/hinic3_queue_common.c

Extension

.c

Size

1658 bytes

Lines

68

Domain

Driver Families

Bucket

drivers/net

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Allocates kernel memory; connect allocation flags and lifetime to context constraints.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/device.h
• hinic3_hwdev.h
• hinic3_queue_common.h

Detected Declarations

• function hinic3_queue_pages_init
• function __queue_pages_free
• function hinic3_queue_pages_free
• function hinic3_queue_pages_alloc

Annotated Snippet

if (err) {
			__queue_pages_free(hwdev, qpages, pg_idx);
			return err;
		}
	}

	return 0;
}

Annotation

• Immediate include surface: `linux/device.h`, `hinic3_hwdev.h`, `hinic3_queue_common.h`.
• Detected declarations: `function hinic3_queue_pages_init`, `function __queue_pages_free`, `function hinic3_queue_pages_free`, `function hinic3_queue_pages_alloc`.
• Atlas domain: Driver Families / drivers/net.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.