drivers/net/ethernet/huawei/hinic3/hinic3_tx.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/huawei/hinic3/hinic3_tx.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/huawei/hinic3/hinic3_tx.h
Extension
.h
Size
4724 bytes
Lines
164
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hinic3_sq_wqe_desc {
	__le32 ctrl_len;
	__le32 queue_info;
	__le32 hi_addr;
	__le32 lo_addr;
};

struct hinic3_sq_task {
	__le32 pkt_info0;
	__le32 ip_identify;
	__le32 rsvd;
	__le32 vlan_offload;
};

struct hinic3_sq_wqe_combo {
	struct hinic3_sq_wqe_desc *ctrl_bd0;
	struct hinic3_sq_task     *task;
	struct hinic3_sq_bufdesc  *bds_head;
	struct hinic3_sq_bufdesc  *bds_sec2;
	u16                       first_bds_num;
	u32                       wqe_type;
	u32                       task_type;
};

struct hinic3_txq_stats {
	u64                   packets;
	u64                   bytes;
	u64                   busy;
	u64                   dropped;
	u64                   skb_pad_err;
	u64                   frag_len_overflow;
	u64                   offload_cow_skb_err;
	u64                   map_frag_err;
	u64                   unknown_tunnel_pkt;
	u64                   frag_size_err;
	struct u64_stats_sync syncp;
};

struct hinic3_dma_info {
	dma_addr_t dma;
	u32        len;
};

struct hinic3_tx_info {
	struct sk_buff         *skb;
	u16                    wqebb_cnt;
	struct hinic3_dma_info *dma_info;
};

struct hinic3_txq {
	struct net_device       *netdev;
	struct device           *dev;

	u16                     q_id;
	u16                     tx_stop_thrs;
	u16                     tx_start_thrs;
	u32                     q_mask;
	u32                     q_depth;

	struct hinic3_tx_info   *tx_info;
	struct hinic3_io_queue  *sq;

	struct hinic3_txq_stats txq_stats;
} ____cacheline_aligned;

struct hinic3_dyna_txq_res {
	struct hinic3_tx_info  *tx_info;
	struct hinic3_dma_info *bds;
};

int hinic3_alloc_txqs(struct net_device *netdev);
void hinic3_free_txqs(struct net_device *netdev);

int hinic3_alloc_txqs_res(struct net_device *netdev, u16 num_sq,
			  u32 sq_depth, struct hinic3_dyna_txq_res *txqs_res);
void hinic3_free_txqs_res(struct net_device *netdev, u16 num_sq,
			  u32 sq_depth, struct hinic3_dyna_txq_res *txqs_res);
int hinic3_configure_txqs(struct net_device *netdev, u16 num_sq,
			  u32 sq_depth, struct hinic3_dyna_txq_res *txqs_res);

netdev_tx_t hinic3_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
bool hinic3_tx_poll(struct hinic3_txq *txq, int budget);
void hinic3_flush_txqs(struct net_device *netdev);

#endif

Annotation

Implementation Notes