drivers/net/ethernet/ibm/ehea/ehea_phyp.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/ibm/ehea/ehea_phyp.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/ibm/ehea/ehea_phyp.h
Extension
.h
Size
12738 bytes
Lines
434
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hcp_modify_qp_cb0 {
	u64 qp_ctl_reg;		/* 00 */
	u32 max_swqe;		/* 02 */
	u32 max_rwqe;		/* 03 */
	u32 port_nb;		/* 04 */
	u32 reserved0;		/* 05 */
	u64 qp_aer;		/* 06 */
	u64 qp_tenure;		/* 08 */
};

/* Hcall Query/Modify Queue Pair Control Block 0 Selection Mask Bits */
#define H_QPCB0_ALL             EHEA_BMASK_IBM(0, 5)
#define H_QPCB0_QP_CTL_REG      EHEA_BMASK_IBM(0, 0)
#define H_QPCB0_MAX_SWQE        EHEA_BMASK_IBM(1, 1)
#define H_QPCB0_MAX_RWQE        EHEA_BMASK_IBM(2, 2)
#define H_QPCB0_PORT_NB         EHEA_BMASK_IBM(3, 3)
#define H_QPCB0_QP_AER          EHEA_BMASK_IBM(4, 4)
#define H_QPCB0_QP_TENURE       EHEA_BMASK_IBM(5, 5)

/* Queue Pair Control Register Status Bits */
#define H_QP_CR_ENABLED		    0x8000000000000000ULL /* QP enabled */
							  /* QP States: */
#define H_QP_CR_STATE_RESET	    0x0000010000000000ULL /*  Reset */
#define H_QP_CR_STATE_INITIALIZED   0x0000020000000000ULL /*  Initialized */
#define H_QP_CR_STATE_RDY2RCV	    0x0000030000000000ULL /*  Ready to recv */
#define H_QP_CR_STATE_RDY2SND	    0x0000050000000000ULL /*  Ready to send */
#define H_QP_CR_STATE_ERROR	    0x0000800000000000ULL /*  Error */
#define H_QP_CR_RES_STATE 	    0x0000007F00000000ULL /* Resultant state */

struct hcp_modify_qp_cb1 {
	u32 qpn;		/* 00 */
	u32 qp_asyn_ev_eq_nb;	/* 01 */
	u64 sq_cq_handle;	/* 02 */
	u64 rq_cq_handle;	/* 04 */
	/* sgel = scatter gather element */
	u32 sgel_nb_sq;		/* 06 */
	u32 sgel_nb_rq1;	/* 07 */
	u32 sgel_nb_rq2;	/* 08 */
	u32 sgel_nb_rq3;	/* 09 */
};

/* Hcall Query/Modify Queue Pair Control Block 1 Selection Mask Bits */
#define H_QPCB1_ALL             EHEA_BMASK_IBM(0, 7)
#define H_QPCB1_QPN             EHEA_BMASK_IBM(0, 0)
#define H_QPCB1_ASYN_EV_EQ_NB   EHEA_BMASK_IBM(1, 1)
#define H_QPCB1_SQ_CQ_HANDLE    EHEA_BMASK_IBM(2, 2)
#define H_QPCB1_RQ_CQ_HANDLE    EHEA_BMASK_IBM(3, 3)
#define H_QPCB1_SGEL_NB_SQ      EHEA_BMASK_IBM(4, 4)
#define H_QPCB1_SGEL_NB_RQ1     EHEA_BMASK_IBM(5, 5)
#define H_QPCB1_SGEL_NB_RQ2     EHEA_BMASK_IBM(6, 6)
#define H_QPCB1_SGEL_NB_RQ3     EHEA_BMASK_IBM(7, 7)

struct hcp_query_ehea {
	u32 cur_num_qps;		/* 00 */
	u32 cur_num_cqs;		/* 01 */
	u32 cur_num_eqs;		/* 02 */
	u32 cur_num_mrs;		/* 03 */
	u32 auth_level;			/* 04 */
	u32 max_num_qps;		/* 05 */
	u32 max_num_cqs;		/* 06 */
	u32 max_num_eqs;		/* 07 */
	u32 max_num_mrs;		/* 08 */
	u32 reserved0;			/* 09 */
	u32 int_clock_freq;		/* 10 */
	u32 max_num_pds;		/* 11 */
	u32 max_num_addr_handles;	/* 12 */
	u32 max_num_cqes;		/* 13 */
	u32 max_num_wqes;		/* 14 */
	u32 max_num_sgel_rq1wqe;	/* 15 */
	u32 max_num_sgel_rq2wqe;	/* 16 */
	u32 max_num_sgel_rq3wqe;	/* 17 */
	u32 mr_page_size;		/* 18 */
	u32 reserved1;			/* 19 */
	u64 max_mr_size;		/* 20 */
	u64 reserved2;			/* 22 */
	u32 num_ports;			/* 24 */
	u32 reserved3;			/* 25 */
	u32 reserved4;			/* 26 */
	u32 reserved5;			/* 27 */
	u64 max_mc_mac;			/* 28 */
	u64 ehea_cap;			/* 30 */
	u32 max_isn_per_eq;		/* 32 */
	u32 max_num_neq;		/* 33 */
	u64 max_num_vlan_ids;		/* 34 */
	u32 max_num_port_group;		/* 36 */
	u32 max_num_phys_port;		/* 37 */

};

/* Hcall Query/Modify Port Control Block defines */

Annotation

Implementation Notes