drivers/net/ethernet/ibm/emac/mal.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/ibm/emac/mal.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/ibm/emac/mal.h
Extension
.h
Size
8577 bytes
Lines
308
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mal_descriptor {
	u16 ctrl;		/* MAL / Commac status control bits */
	u16 data_len;		/* Max length is 4K-1 (12 bits)     */
	u32 data_ptr;		/* pointer to actual data buffer    */
};

/* the following defines are for the MadMAL status and control registers. */
/* MADMAL transmit and receive status/control bits  */
#define MAL_RX_CTRL_EMPTY	0x8000
#define MAL_RX_CTRL_WRAP	0x4000
#define MAL_RX_CTRL_CM		0x2000
#define MAL_RX_CTRL_LAST	0x1000
#define MAL_RX_CTRL_FIRST	0x0800
#define MAL_RX_CTRL_INTR	0x0400
#define MAL_RX_CTRL_SINGLE	(MAL_RX_CTRL_LAST | MAL_RX_CTRL_FIRST)
#define MAL_IS_SINGLE_RX(ctrl)	(((ctrl) & MAL_RX_CTRL_SINGLE) == MAL_RX_CTRL_SINGLE)

#define MAL_TX_CTRL_READY	0x8000
#define MAL_TX_CTRL_WRAP	0x4000
#define MAL_TX_CTRL_CM		0x2000
#define MAL_TX_CTRL_LAST	0x1000
#define MAL_TX_CTRL_INTR	0x0400

struct mal_commac_ops {
	void	(*poll_tx) (void *dev);
	int	(*poll_rx) (void *dev, int budget);
	int	(*peek_rx) (void *dev);
	void	(*rxde) (void *dev);
};

struct mal_commac {
	struct mal_commac_ops	*ops;
	void			*dev;
	struct list_head	poll_list;
	long       		flags;
#define MAL_COMMAC_RX_STOPPED		0
#define MAL_COMMAC_POLL_DISABLED	1
	u32			tx_chan_mask;
	u32			rx_chan_mask;
	struct list_head	list;
};

struct mal_instance {
	int			version;
	dcr_host_t		dcr_host;

	int			num_tx_chans;	/* Number of TX channels */
	int			num_rx_chans;	/* Number of RX channels */
	int 			txeob_irq;	/* TX End Of Buffer IRQ  */
	int 			rxeob_irq;	/* RX End Of Buffer IRQ  */
	int			txde_irq;	/* TX Descriptor Error IRQ */
	int			rxde_irq;	/* RX Descriptor Error IRQ */
	int			serr_irq;	/* MAL System Error IRQ    */

	struct list_head	poll_list;
	struct napi_struct	napi;

	struct list_head	list;
	u32			tx_chan_mask;
	u32			rx_chan_mask;

	dma_addr_t		bd_dma;
	struct mal_descriptor	*bd_virt;

	struct platform_device	*ofdev;
	int			index;
	spinlock_t		lock;

	struct net_device	*dummy_dev;

	unsigned int features;
};

static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg)
{
	return dcr_read(mal->dcr_host, reg);
}

static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val)
{
	dcr_write(mal->dcr_host, reg, val);
}

/* Features of various MAL implementations */

/* Set if you have interrupt coalescing and you have to clear the SDR
 * register for TXEOB and RXEOB interrupts to work
 */
#define MAL_FTR_CLEAR_ICINTSTAT	0x00000001

Annotation

Implementation Notes