drivers/net/ethernet/intel/e1000e/80003es2lan.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/intel/e1000e/80003es2lan.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/intel/e1000e/80003es2lan.c
Extension
.c
Size
37363 bytes
Lines
1412
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
			e1000_release_phy_80003es2lan(hw);
			return -E1000_ERR_PHY;
		}

		usleep_range(200, 400);

		ret_val = e1000e_read_phy_reg_mdic(hw,
						   MAX_PHY_REG_ADDRESS & offset,
						   data);

		usleep_range(200, 400);
	} else {
		ret_val = e1000e_read_phy_reg_mdic(hw,
						   MAX_PHY_REG_ADDRESS & offset,
						   data);
	}

	e1000_release_phy_80003es2lan(hw);

	return ret_val;
}

/**
 *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 *  @hw: pointer to the HW structure
 *  @offset: offset of the register to read
 *  @data: value to write to the register
 *
 *  Write to the GG82563 PHY register.
 **/
static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
						   u32 offset, u16 data)
{
	s32 ret_val;
	u32 page_select;
	u16 temp;

	ret_val = e1000_acquire_phy_80003es2lan(hw);
	if (ret_val)
		return ret_val;

	/* Select Configuration Page */
	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
		page_select = GG82563_PHY_PAGE_SELECT;
	} else {
		/* Use Alternative Page Select register to access
		 * registers 30 and 31
		 */
		page_select = GG82563_PHY_PAGE_SELECT_ALT;
	}

	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
	if (ret_val) {
		e1000_release_phy_80003es2lan(hw);
		return ret_val;
	}

	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
		/* The "ready" bit in the MDIC register may be incorrectly set
		 * before the device has completed the "Page Select" MDI
		 * transaction.  So we wait 200us after each MDI command...
		 */
		usleep_range(200, 400);

		/* ...and verify the command was successful. */
		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);

		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
			e1000_release_phy_80003es2lan(hw);
			return -E1000_ERR_PHY;
		}

		usleep_range(200, 400);

		ret_val = e1000e_write_phy_reg_mdic(hw,
						    MAX_PHY_REG_ADDRESS &
						    offset, data);

		usleep_range(200, 400);
	} else {
		ret_val = e1000e_write_phy_reg_mdic(hw,
						    MAX_PHY_REG_ADDRESS &
						    offset, data);
	}

	e1000_release_phy_80003es2lan(hw);

	return ret_val;

Annotation

Implementation Notes