drivers/net/ethernet/intel/e1000e/ich8lan.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/intel/e1000e/ich8lan.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/intel/e1000e/ich8lan.h
Extension
.h
Size
13001 bytes
Lines
314
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _E1000E_ICH8LAN_H_
#define _E1000E_ICH8LAN_H_

#define ICH_FLASH_GFPREG		0x0000
#define ICH_FLASH_HSFSTS		0x0004
#define ICH_FLASH_HSFCTL		0x0006
#define ICH_FLASH_FADDR			0x0008
#define ICH_FLASH_FDATA0		0x0010
#define ICH_FLASH_PR0			0x0074

/* Requires up to 10 seconds when MNG might be accessing part. */
#define ICH_FLASH_READ_COMMAND_TIMEOUT	10000000
#define ICH_FLASH_WRITE_COMMAND_TIMEOUT	10000000
#define ICH_FLASH_ERASE_COMMAND_TIMEOUT	10000000
#define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF
#define ICH_FLASH_CYCLE_REPEAT_COUNT	10

#define ICH_CYCLE_READ			0
#define ICH_CYCLE_WRITE			2
#define ICH_CYCLE_ERASE			3

#define FLASH_GFPREG_BASE_MASK		0x1FFF
#define FLASH_SECTOR_ADDR_SHIFT		12

#define ICH_FLASH_SEG_SIZE_256		256
#define ICH_FLASH_SEG_SIZE_4K		4096
#define ICH_FLASH_SEG_SIZE_8K		8192
#define ICH_FLASH_SEG_SIZE_64K		65536

#define E1000_ICH_FWSM_RSPCIPHY	0x00000040	/* Reset PHY on PCI Reset */
/* FW established a valid mode */
#define E1000_ICH_FWSM_FW_VALID	0x00008000
#define E1000_ICH_FWSM_PCIM2PCI	0x01000000	/* ME PCIm-to-PCI active */
#define E1000_ICH_FWSM_PCIM2PCI_COUNT	2000

#define E1000_ICH_MNG_IAMT_MODE		0x2

#define E1000_FWSM_WLOCK_MAC_MASK	0x0380
#define E1000_FWSM_WLOCK_MAC_SHIFT	7
#define E1000_FWSM_ULP_CFG_DONE		0x00000400	/* Low power cfg done */
#define E1000_EXFWSM_DPG_EXIT_DONE	0x00000001

/* Shared Receive Address Registers */
#define E1000_SHRAL_PCH_LPT(_i)		(0x05408 + ((_i) * 8))
#define E1000_SHRAH_PCH_LPT(_i)		(0x0540C + ((_i) * 8))

#define E1000_H2ME		0x05B50	/* Host to ME */
#define E1000_H2ME_START_DPG	0x00000001	/* indicate the ME of DPG */
#define E1000_H2ME_EXIT_DPG	0x00000002	/* indicate the ME exit DPG */
#define E1000_H2ME_ULP		0x00000800	/* ULP Indication Bit */
#define E1000_H2ME_ENFORCE_SETTINGS	0x00001000	/* Enforce Settings */

#define ID_LED_DEFAULT_ICH8LAN	((ID_LED_DEF1_DEF2 << 12) | \
				 (ID_LED_OFF1_OFF2 <<  8) | \
				 (ID_LED_OFF1_ON2  <<  4) | \
				 (ID_LED_DEF1_DEF2))

#define E1000_ICH_NVM_SIG_WORD		0x13u
#define E1000_ICH_NVM_SIG_MASK		0xC000u
#define E1000_ICH_NVM_VALID_SIG_MASK	0xC0u
#define E1000_ICH_NVM_SIG_VALUE		0x80u

#define E1000_ICH8_LAN_INIT_TIMEOUT	1500

/* FEXT register bit definition */
#define E1000_FEXT_PHY_CABLE_DISCONNECTED	0x00000004

#define E1000_FEXTNVM_SW_CONFIG		1
#define E1000_FEXTNVM_SW_CONFIG_ICH8M	(1 << 27)	/* different on ICH8M */

#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK	0x0C000000
#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC	0x08000000

#define E1000_FEXTNVM4_BEACON_DURATION_MASK	0x7
#define E1000_FEXTNVM4_BEACON_DURATION_8USEC	0x7
#define E1000_FEXTNVM4_BEACON_DURATION_16USEC	0x3

#define E1000_FEXTNVM6_REQ_PLL_CLK	0x00000100
#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION	0x00000200
#define E1000_FEXTNVM6_K1_OFF_ENABLE	0x80000000
/* bit for disabling packet buffer read */
#define E1000_FEXTNVM7_DISABLE_PB_READ	0x00040000
#define E1000_FEXTNVM7_SIDE_CLK_UNGATE	0x00000004
#define E1000_FEXTNVM7_DISABLE_SMB_PERST	0x00000020
#define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS	0x00000800
#define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS	0x00001000
#define E1000_FEXTNVM11_DISABLE_PB_READ		0x00000200
#define E1000_FEXTNVM11_DISABLE_MULR_FIX	0x00002000

/* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */

Annotation

Implementation Notes