drivers/net/ethernet/intel/e1000e/phy.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/intel/e1000e/phy.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/intel/e1000e/phy.c
Extension
.c
Size
89762 bytes
Lines
3285
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (!(mdic & E1000_MDIC_READY)) {
			e_dbg("MDI Read PHY Reg Address %d did not complete\n",
			      offset);
			success = false;
		}
		if (mdic & E1000_MDIC_ERROR) {
			e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
			success = false;
		}
		if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
			e_dbg("MDI Read offset error - requested %d, returned %d\n",
			      offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
			success = false;
		}

		/* Allow some time after each MDIC transaction to avoid
		 * reading duplicate data in the next MDIC transaction.
		 */
		if (hw->mac.type == e1000_pch2lan)
			udelay(100);

		if (success) {
			*data = (u16)mdic;
			return 0;
		}

		if (retry_counter != retry_max) {
			e_dbg("Perform retry on PHY transaction...\n");
			mdelay(10);
		}
	}

	return -E1000_ERR_PHY;
}

/**
 *  e1000e_write_phy_reg_mdic - Write MDI control register
 *  @hw: pointer to the HW structure
 *  @offset: register offset to write to
 *  @data: data to write to register at offset
 *
 *  Writes data to MDI control register in the PHY at offset.
 **/
s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
{
	u32 i, mdic = 0, retry_counter, retry_max;
	struct e1000_phy_info *phy = &hw->phy;
	bool success;

	if (offset > MAX_PHY_REG_ADDRESS) {
		e_dbg("PHY Address %d is out of range\n", offset);
		return -E1000_ERR_PARAM;
	}

	retry_max = phy->retry_enabled ? phy->retry_count : 0;

	/* Set up Op-code, Phy Address, and register offset in the MDI
	 * Control register.  The MAC will take care of interfacing with the
	 * PHY to retrieve the desired data.
	 */
	for (retry_counter = 0; retry_counter <= retry_max; retry_counter++) {
		success = true;

		mdic = (((u32)data) |
			(offset << E1000_MDIC_REG_SHIFT) |
			(phy->addr << E1000_MDIC_PHY_SHIFT) |
			(E1000_MDIC_OP_WRITE));

		ew32(MDIC, mdic);

		/* Poll the ready bit to see if the MDI read completed
		 * Increasing the time out as testing showed failures with
		 * the lower time out
		 */
		for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
			udelay(50);
			mdic = er32(MDIC);
			if (mdic & E1000_MDIC_READY)
				break;
		}
		if (!(mdic & E1000_MDIC_READY)) {
			e_dbg("MDI Write PHY Reg Address %d did not complete\n",
			      offset);
			success = false;
		}
		if (mdic & E1000_MDIC_ERROR) {
			e_dbg("MDI Write PHY Reg Address %d Error\n", offset);
			success = false;
		}
		if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {

Annotation

Implementation Notes