drivers/net/ethernet/intel/ice/ice_common.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/intel/ice/ice_common.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/intel/ice/ice_common.c- Extension
.c- Size
- 188552 bytes
- Lines
- 6564
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
ice_common.hice_sched.hice_adminq_cmd.hice_flow.hice_ptp_hw.hlinux/packing.h
Detected Declarations
function ice_dump_phy_typefunction ice_set_mac_typefunction ice_is_generic_macfunction configurationfunction addressfunction Portfunction typefunction ice_aq_get_netlist_nodefunction ice_find_netlist_nodefunction ice_is_media_cage_presentfunction ice_get_media_typefunction ice_get_link_status_datalenfunction Statusfunction ice_fill_tx_timer_and_fc_threshfunction configurationfunction ice_init_fltr_mgmt_structfunction ice_cleanup_fltr_mgmt_structfunction list_for_each_entry_safefunction list_for_each_entry_safefunction list_for_each_entry_safefunction ice_get_itr_intrl_granfunction ice_wait_fw_loadfunction __fwlog_send_cmdfunction __fwlog_initfunction ice_init_hwfunction __fwlog_deinitfunction ice_init_hwfunction ice_check_resetfunction ice_pf_resetfunction ice_resetfunction ice_copy_rxq_ctx_to_hwfunction ice_copy_rxq_ctx_from_hwfunction ice_pack_rxq_ctxfunction ice_unpack_rxq_ctxfunction ice_write_rxq_ctxfunction ice_read_rxq_ctxfunction ice_pack_txq_ctxfunction ice_pack_txq_ctx_fullfunction bufferfunction ice_copy_txq_ctx_from_hwfunction ice_copy_txq_ctx_to_hwfunction ice_read_txq_ctxfunction ice_write_txq_ctxfunction ice_pack_txtime_ctxfunction ice_sbq_send_cmdfunction ice_sbq_rw_regfunction ice_should_retry_sq_send_cmdfunction ice_sq_send_cmd_retry
Annotated Snippet
if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
ether_addr_copy(hw->port_info->mac.lan_addr,
resp[i].mac_addr);
ether_addr_copy(hw->port_info->mac.perm_addr,
resp[i].mac_addr);
break;
}
return 0;
}
/**
* ice_aq_get_phy_caps - returns PHY capabilities
* @pi: port information structure
* @qual_mods: report qualified modules
* @report_mode: report mode capabilities
* @pcaps: structure for PHY capabilities to be filled
* @cd: pointer to command details structure or NULL
*
* Returns the various PHY capabilities supported on the Port (0x0600)
*/
int
ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
struct ice_aqc_get_phy_caps_data *pcaps,
struct ice_sq_cd *cd)
{
struct ice_aqc_get_phy_caps *cmd;
u16 pcaps_size = sizeof(*pcaps);
struct libie_aq_desc desc;
const char *prefix;
struct ice_hw *hw;
int status;
cmd = libie_aq_raw(&desc);
if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
return -EINVAL;
hw = pi->hw;
if (report_mode == ICE_AQC_REPORT_DFLT_CFG &&
!ice_fw_supports_report_dflt_cfg(hw))
return -EINVAL;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
if (qual_mods)
cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM);
cmd->param0 |= cpu_to_le16(report_mode);
status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n");
switch (report_mode) {
case ICE_AQC_REPORT_TOPO_CAP_MEDIA:
prefix = "phy_caps_media";
break;
case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA:
prefix = "phy_caps_no_media";
break;
case ICE_AQC_REPORT_ACTIVE_CFG:
prefix = "phy_caps_active";
break;
case ICE_AQC_REPORT_DFLT_CFG:
prefix = "phy_caps_default";
break;
default:
prefix = "phy_caps_invalid";
}
ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low),
le64_to_cpu(pcaps->phy_type_high), prefix);
ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n",
prefix, report_mode);
ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps);
ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix,
pcaps->low_power_ctrl_an);
ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix,
pcaps->eee_cap);
ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix,
pcaps->eeer_value);
ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix,
pcaps->link_fec_options);
ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n",
prefix, pcaps->module_compliance_enforcement);
ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n",
prefix, pcaps->extended_compliance_code);
ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix,
pcaps->module_type[0]);
Annotation
- Immediate include surface: `ice_common.h`, `ice_sched.h`, `ice_adminq_cmd.h`, `ice_flow.h`, `ice_ptp_hw.h`, `linux/packing.h`.
- Detected declarations: `function ice_dump_phy_type`, `function ice_set_mac_type`, `function ice_is_generic_mac`, `function configuration`, `function address`, `function Port`, `function type`, `function ice_aq_get_netlist_node`, `function ice_find_netlist_node`, `function ice_is_media_cage_present`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.