drivers/net/ethernet/intel/ice/ice_common.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/intel/ice/ice_common.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/intel/ice/ice_common.h
Extension
.h
Size
14112 bytes
Lines
365
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _ICE_COMMON_H_
#define _ICE_COMMON_H_

#include <linux/bitfield.h>

#include "ice.h"
#include "ice_type.h"
#include "ice_nvm.h"
#include "ice_flex_pipe.h"
#include "ice_parser.h"
#include <linux/avf/virtchnl.h>
#include "ice_switch.h"
#include "ice_fdir.h"

#define ICE_SQ_SEND_DELAY_TIME_MS	10
#define ICE_SQ_SEND_MAX_EXECUTE		3

#define FEC_REG_SHIFT 2
#define FEC_RECV_ID_SHIFT 4
#define FEC_CORR_LOW_REG_PORT0 (0x02 << FEC_REG_SHIFT)
#define FEC_CORR_HIGH_REG_PORT0 (0x03 << FEC_REG_SHIFT)
#define FEC_UNCORR_LOW_REG_PORT0 (0x04 << FEC_REG_SHIFT)
#define FEC_UNCORR_HIGH_REG_PORT0 (0x05 << FEC_REG_SHIFT)
#define FEC_CORR_LOW_REG_PORT1 (0x42 << FEC_REG_SHIFT)
#define FEC_CORR_HIGH_REG_PORT1 (0x43 << FEC_REG_SHIFT)
#define FEC_UNCORR_LOW_REG_PORT1 (0x44 << FEC_REG_SHIFT)
#define FEC_UNCORR_HIGH_REG_PORT1 (0x45 << FEC_REG_SHIFT)
#define FEC_CORR_LOW_REG_PORT2 (0x4A << FEC_REG_SHIFT)
#define FEC_CORR_HIGH_REG_PORT2 (0x4B << FEC_REG_SHIFT)
#define FEC_UNCORR_LOW_REG_PORT2 (0x4C << FEC_REG_SHIFT)
#define FEC_UNCORR_HIGH_REG_PORT2 (0x4D << FEC_REG_SHIFT)
#define FEC_CORR_LOW_REG_PORT3 (0x52 << FEC_REG_SHIFT)
#define FEC_CORR_HIGH_REG_PORT3 (0x53 << FEC_REG_SHIFT)
#define FEC_UNCORR_LOW_REG_PORT3 (0x54 << FEC_REG_SHIFT)
#define FEC_UNCORR_HIGH_REG_PORT3 (0x55 << FEC_REG_SHIFT)
#define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT)
#define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT)

#define ICE_CGU_R9			0x24
#define ICE_CGU_R9_TIME_REF_FREQ_SEL	GENMASK(2, 0)
#define ICE_CGU_R9_CLK_EREF0_EN		BIT(4)
#define ICE_CGU_R9_TIME_REF_EN		BIT(5)
#define ICE_CGU_R9_TIME_SYNC_EN		BIT(6)
#define ICE_CGU_R9_ONE_PPS_OUT_EN	BIT(7)
#define ICE_CGU_R9_ONE_PPS_OUT_AMP	GENMASK(19, 18)

#define ICE_CGU_R16			0x40
#define ICE_CGU_R16_TSPLL_CK_REFCLKFREQ	GENMASK(31, 24)

#define ICE_CGU_R19			0x4C
#define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E82X	GENMASK(7, 0)
#define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E825	GENMASK(9, 0)
#define ICE_CGU_R19_TSPLL_NDIVRATIO	GENMASK(19, 16)

#define ICE_CGU_R22			0x58
#define ICE_CGU_R22_TIME1588CLK_DIV	GENMASK(23, 20)
#define ICE_CGU_R22_TIME1588CLK_DIV2	BIT(30)

#define ICE_CGU_R23			0x5C
#define ICE_CGU_R24			0x60
#define ICE_CGU_R24_FBDIV_FRAC		GENMASK(21, 0)
#define ICE_CGU_R23_R24_TSPLL_ENABLE	BIT(24)
#define ICE_CGU_R23_R24_REF1588_CK_DIV	GENMASK(30, 27)
#define ICE_CGU_R23_R24_TIME_REF_SEL	BIT(31)

#define ICE_CGU_BW_TDC			0x31C
#define ICE_CGU_BW_TDC_PLLLOCK_SEL	GENMASK(30, 29)

#define ICE_CGU_RO_LOCK			0x3F0
#define ICE_CGU_RO_LOCK_TRUE_LOCK	BIT(12)
#define ICE_CGU_RO_LOCK_UNLOCK		BIT(13)

#define ICE_CGU_CNTR_BIST		0x344
#define ICE_CGU_CNTR_BIST_PLLLOCK_SEL_0	BIT(15)
#define ICE_CGU_CNTR_BIST_PLLLOCK_SEL_1	BIT(16)

#define ICE_CGU_RO_BWM_LF		0x370
#define ICE_CGU_RO_BWM_LF_TRUE_LOCK	BIT(12)

int ice_init_hw(struct ice_hw *hw);
void ice_deinit_hw(struct ice_hw *hw);
int ice_check_reset(struct ice_hw *hw);
int ice_reset(struct ice_hw *hw, enum ice_reset_req req);
int ice_create_all_ctrlq(struct ice_hw *hw);
int ice_init_all_ctrlq(struct ice_hw *hw);
void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading);
void ice_destroy_all_ctrlq(struct ice_hw *hw);
int
ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
		  struct ice_rq_event_info *e, u16 *pending);

Annotation

Implementation Notes