drivers/net/ethernet/intel/ice/ice_hw_autogen.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/intel/ice/ice_hw_autogen.h

File Facts

System: Linux kernel
Corpus path: drivers/net/ethernet/intel/ice/ice_hw_autogen.h
Extension: .h
Size: 26039 bytes
Lines: 582
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _ICE_HW_AUTOGEN_H_
#define _ICE_HW_AUTOGEN_H_

#define GLCOMM_QUANTA_PROF(_i)			(0x002D2D68 + ((_i) * 4))
#define GLCOMM_QUANTA_PROF_MAX_INDEX		15
#define GLCOMM_QUANTA_PROF_QUANTA_SIZE_S	0
#define GLCOMM_QUANTA_PROF_QUANTA_SIZE_M	ICE_M(0x3FFF, 0)
#define GLCOMM_QUANTA_PROF_MAX_CMD_S		16
#define GLCOMM_QUANTA_PROF_MAX_CMD_M		ICE_M(0xFF, 16)
#define GLCOMM_QUANTA_PROF_MAX_DESC_S		24
#define GLCOMM_QUANTA_PROF_MAX_DESC_M		ICE_M(0x3F, 24)
#define QTX_COMM_DBELL(_DBQM)			(0x002C0000 + ((_DBQM) * 4))
#define QTX_COMM_HEAD(_DBQM)			(0x000E0000 + ((_DBQM) * 4))
#define QTX_COMM_HEAD_MAX_INDEX			16383
#define QTX_COMM_HEAD_HEAD_S			0
#define QTX_COMM_HEAD_HEAD_M			ICE_M(0x1FFF, 0)
#define E830_GLQTX_TXTIME_DBELL_LSB(_DBQM)	(0x002E0000 + ((_DBQM) * 8))
#define PF_FW_ARQBAH				0x00080180
#define PF_FW_ARQBAL				0x00080080
#define PF_FW_ARQH				0x00080380
#define PF_FW_ARQH_ARQH_M			ICE_M(0x3FF, 0)
#define PF_FW_ARQLEN				0x00080280
#define PF_FW_ARQLEN_ARQLEN_M			ICE_M(0x3FF, 0)
#define PF_FW_ARQLEN_ARQVFE_M			BIT(28)
#define PF_FW_ARQLEN_ARQOVFL_M			BIT(29)
#define PF_FW_ARQLEN_ARQCRIT_M			BIT(30)
#define PF_FW_ARQLEN_ARQENABLE_M		BIT(31)
#define PF_FW_ARQT				0x00080480
#define PF_FW_ATQBAH				0x00080100
#define PF_FW_ATQBAL				0x00080000
#define PF_FW_ATQH				0x00080300
#define PF_FW_ATQH_ATQH_M			ICE_M(0x3FF, 0)
#define PF_FW_ATQLEN				0x00080200
#define PF_FW_ATQLEN_ATQLEN_M			ICE_M(0x3FF, 0)
#define PF_FW_ATQLEN_ATQVFE_M			BIT(28)
#define PF_FW_ATQLEN_ATQOVFL_M			BIT(29)
#define PF_FW_ATQLEN_ATQCRIT_M			BIT(30)
#define VF_MBX_ARQLEN(_VF)			(0x0022BC00 + ((_VF) * 4))
#define VF_MBX_ATQLEN(_VF)			(0x0022A800 + ((_VF) * 4))
#define PF_FW_ATQLEN_ATQENABLE_M		BIT(31)
#define PF_FW_ATQT				0x00080400
#define PF_MBX_ARQBAH				0x0022E400
#define PF_MBX_ARQBAL				0x0022E380
#define PF_MBX_ARQH				0x0022E500
#define PF_MBX_ARQH_ARQH_M			ICE_M(0x3FF, 0)
#define PF_MBX_ARQLEN				0x0022E480
#define PF_MBX_ARQLEN_ARQLEN_M			ICE_M(0x3FF, 0)
#define PF_MBX_ARQLEN_ARQCRIT_M			BIT(30)
#define PF_MBX_ARQLEN_ARQENABLE_M		BIT(31)
#define PF_MBX_ARQT				0x0022E580
#define PF_MBX_ATQBAH				0x0022E180
#define PF_MBX_ATQBAL				0x0022E100
#define PF_MBX_ATQH				0x0022E280
#define PF_MBX_ATQH_ATQH_M			ICE_M(0x3FF, 0)
#define PF_MBX_ATQLEN				0x0022E200
#define PF_MBX_ATQLEN_ATQLEN_M			ICE_M(0x3FF, 0)
#define PF_MBX_ATQLEN_ATQCRIT_M			BIT(30)
#define PF_MBX_ATQLEN_ATQENABLE_M		BIT(31)
#define PF_MBX_ATQT				0x0022E300
#define PF_SB_ARQBAH				0x0022FF00
#define PF_SB_ARQBAH_ARQBAH_S			0
#define PF_SB_ARQBAH_ARQBAH_M			ICE_M(0xFFFFFFFF, 0)
#define PF_SB_ARQBAL				0x0022FE80
#define PF_SB_ARQBAL_ARQBAL_LSB_S		0
#define PF_SB_ARQBAL_ARQBAL_LSB_M		ICE_M(0x3F, 0)
#define PF_SB_ARQBAL_ARQBAL_S			6
#define PF_SB_ARQBAL_ARQBAL_M			ICE_M(0x3FFFFFF, 6)
#define PF_SB_ARQH				0x00230000
#define PF_SB_ARQH_ARQH_S			0
#define PF_SB_ARQH_ARQH_M			ICE_M(0x3FF, 0)
#define PF_SB_ARQLEN				0x0022FF80
#define PF_SB_ARQLEN_ARQLEN_S			0
#define PF_SB_ARQLEN_ARQLEN_M			ICE_M(0x3FF, 0)
#define PF_SB_ARQLEN_ARQVFE_S			28
#define PF_SB_ARQLEN_ARQVFE_M			BIT(28)
#define PF_SB_ARQLEN_ARQOVFL_S			29
#define PF_SB_ARQLEN_ARQOVFL_M			BIT(29)
#define PF_SB_ARQLEN_ARQCRIT_S			30
#define PF_SB_ARQLEN_ARQCRIT_M			BIT(30)
#define PF_SB_ARQLEN_ARQENABLE_S		31
#define PF_SB_ARQLEN_ARQENABLE_M		BIT(31)
#define PF_SB_ARQT				0x00230080
#define PF_SB_ARQT_ARQT_S			0
#define PF_SB_ARQT_ARQT_M			ICE_M(0x3FF, 0)
#define PF_SB_ATQBAH				0x0022FC80
#define PF_SB_ATQBAH_ATQBAH_S			0
#define PF_SB_ATQBAH_ATQBAH_M			ICE_M(0xFFFFFFFF, 0)
#define PF_SB_ATQBAL				0x0022FC00
#define PF_SB_ATQBAL_ATQBAL_S			6
#define PF_SB_ATQBAL_ATQBAL_M			ICE_M(0x3FFFFFF, 6)

Annotation

Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.