drivers/net/ethernet/intel/ice/ice_parser_rt.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/intel/ice/ice_parser_rt.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/intel/ice/ice_parser_rt.c
Extension
.c
Size
22006 bytes
Lines
860
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (alu->dst_start >= ICE_PARSER_ERR_NUM) {
			ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Invalid error %d\n",
				  alu->dst_start);
			return;
		}
		ice_err_add(rt, alu->dst_start, val);
	} else if (alu->dst_reg_id >= ICE_GPR_FLG_IDX) {
		flg_idx = (u16)(((alu->dst_reg_id - ICE_GPR_FLG_IDX) << 4) +
				alu->dst_start);

		if (flg_idx >= ICE_PARSER_FLG_NUM) {
			ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Invalid flag %d\n",
				  flg_idx);
			return;
		}
		ice_flg_add(rt, flg_idx, val);
	} else {
		ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Unexpected Dest Register Bit set, RegisterID %d Start %d\n",
			  alu->dst_reg_id, alu->dst_start);
	}
}

static void ice_alu_exe(struct ice_parser_rt *rt, struct ice_alu *alu)
{
	u16 dst, src, shift, imm;

	if (alu->shift_xlate_sel) {
		ice_debug(rt->psr->hw, ICE_DBG_PARSER, "shift_xlate_sel != 0 is not expected\n");
		return;
	}

	ice_po_update(rt, alu);
	ice_flg_update(rt, alu);

	dst = rt->gpr[alu->dst_reg_id];
	src = ice_reg_bit_sel(rt, alu->src_reg_id,
			      alu->src_start, alu->src_len);
	shift = alu->shift_xlate_key;
	imm = alu->imm;

	switch (alu->opc) {
	case ICE_ALU_PARK:
		break;
	case ICE_ALU_MOV_ADD:
		dst = (src << shift) + imm;
		ice_gpr_add(rt, alu->dst_reg_id, dst);
		break;
	case ICE_ALU_ADD:
		dst += (src << shift) + imm;
		ice_gpr_add(rt, alu->dst_reg_id, dst);
		break;
	case ICE_ALU_ORLT:
		if (src < imm)
			ice_dst_reg_bit_set(rt, alu, true);
		ice_gpr_add(rt, ICE_GPR_NP_IDX, alu->branch_addr);
		break;
	case ICE_ALU_OREQ:
		if (src == imm)
			ice_dst_reg_bit_set(rt, alu, true);
		ice_gpr_add(rt, ICE_GPR_NP_IDX, alu->branch_addr);
		break;
	case ICE_ALU_SETEQ:
		ice_dst_reg_bit_set(rt, alu, src == imm);
		ice_gpr_add(rt, ICE_GPR_NP_IDX, alu->branch_addr);
		break;
	case ICE_ALU_MOV_XOR:
		dst = (src << shift) ^ imm;
		ice_gpr_add(rt, alu->dst_reg_id, dst);
		break;
	default:
		ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Unsupported ALU instruction %d\n",
			  alu->opc);
		break;
	}
}

static void ice_alu0_exe(struct ice_parser_rt *rt)
{
	ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU0 ...\n");
	ice_alu_exe(rt, rt->alu0);
	ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU0 done.\n");
}

static void ice_alu1_exe(struct ice_parser_rt *rt)
{
	ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU1 ...\n");
	ice_alu_exe(rt, rt->alu1);
	ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU1 done.\n");
}

Annotation

Implementation Notes