drivers/net/ethernet/intel/ice/ice_sriov.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/intel/ice/ice_sriov.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/intel/ice/ice_sriov.c- Extension
.c- Size
- 47125 bytes
- Lines
- 1828
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
ice.hice_vf_lib_private.hice_base.hice_lib.hice_fltr.hice_dcb_lib.hice_flow.hice_eswitch.hvirt/allowlist.hice_flex_pipe.hice_vf_vsi_vlan_ops.hice_vlan.h
Detected Declarations
function ice_free_vf_entriesfunction hash_for_each_safefunction ice_free_vf_resfunction ice_dis_vf_mappingsfunction ice_free_vfsfunction ice_for_each_vffunction ice_ena_vf_msix_mappingsfunction ice_ena_vf_q_mappingsfunction ice_ena_vf_mappingsfunction ice_calc_vf_reg_idxfunction ice_set_per_vf_resfunction ice_init_vf_vsi_resfunction ice_start_vfsfunction ice_sriov_free_vffunction ice_sriov_clear_reset_statefunction ice_sriov_clear_mbx_registerfunction ice_sriov_trigger_reset_registerfunction ice_sriov_poll_reset_statusfunction ice_sriov_clear_reset_triggerfunction ice_sriov_post_vsi_rebuildfunction ice_create_vf_entriesfunction ice_ena_vfsfunction ice_pci_sriov_enafunction ice_check_sriov_allowedfunction ice_sriov_get_vf_total_msixfunction ice_sriov_remap_vectorsfunction possiblefunction ice_sriov_configurefunction ice_process_vflr_eventfunction ice_for_each_rxqfunction ice_globalq_to_pfqfunction ice_vf_lan_overflow_eventfunction ice_set_vf_spoofchkfunction ice_get_vf_cfgfunction __ice_set_vf_macfunction ether_addr_equalfunction ice_set_vf_macfunction ice_set_vf_trustfunction ice_set_vf_link_statefunction ice_calc_all_vfs_min_tx_ratefunction ice_min_tx_rate_oversubscribedfunction ice_set_vf_bwfunction ice_get_vf_statsfunction Modefunction ice_set_vf_port_vlanfunction ice_print_vf_rx_mdd_eventfunction ice_print_vf_tx_mdd_eventfunction ice_print_vfs_mdd_events
Annotated Snippet
if (test_bit(ICE_VF_STATE_INIT, vf->vf_states)) {
/* disable VF qp mappings and set VF disable state */
ice_dis_vf_mappings(vf);
set_bit(ICE_VF_STATE_DIS, vf->vf_states);
ice_free_vf_res(vf);
}
if (!pci_vfs_assigned(pf->pdev)) {
u32 reg_idx, bit_idx;
reg_idx = (hw->func_caps.vf_base_id + vf->vf_id) / 32;
bit_idx = (hw->func_caps.vf_base_id + vf->vf_id) % 32;
wr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));
}
mutex_unlock(&vf->cfg_lock);
}
vfs->num_qps_per = 0;
ice_free_vf_entries(pf);
mutex_unlock(&vfs->table_lock);
clear_bit(ICE_VF_DIS, pf->state);
clear_bit(ICE_FLAG_SRIOV_ENA, pf->flags);
}
/**
* ice_vf_vsi_setup - Set up a VF VSI
* @vf: VF to setup VSI for
*
* Returns pointer to the successfully allocated VSI struct on success,
* otherwise returns NULL on failure.
*/
static struct ice_vsi *ice_vf_vsi_setup(struct ice_vf *vf)
{
struct ice_vsi_cfg_params params = {};
struct ice_pf *pf = vf->pf;
struct ice_vsi *vsi;
params.type = ICE_VSI_VF;
params.port_info = ice_vf_get_port_info(vf);
params.vf = vf;
params.flags = ICE_VSI_FLAG_INIT;
vsi = ice_vsi_setup(pf, ¶ms);
if (!vsi) {
dev_err(ice_pf_to_dev(pf), "Failed to create VF VSI\n");
ice_vf_invalidate_vsi(vf);
return NULL;
}
vf->lan_vsi_idx = vsi->idx;
return vsi;
}
/**
* ice_ena_vf_msix_mappings - enable VF MSIX mappings in hardware
* @vf: VF to enable MSIX mappings for
*
* Some of the registers need to be indexed/configured using hardware global
* device values and other registers need 0-based values, which represent PF
* based values.
*/
static void ice_ena_vf_msix_mappings(struct ice_vf *vf)
{
int device_based_first_msix, device_based_last_msix;
int pf_based_first_msix, pf_based_last_msix, v;
struct ice_pf *pf = vf->pf;
int device_based_vf_id;
struct ice_hw *hw;
u32 reg;
hw = &pf->hw;
pf_based_first_msix = vf->first_vector_idx;
pf_based_last_msix = (pf_based_first_msix + vf->num_msix) - 1;
device_based_first_msix = pf_based_first_msix +
pf->hw.func_caps.common_cap.msix_vector_first_id;
device_based_last_msix =
(device_based_first_msix + vf->num_msix) - 1;
device_based_vf_id = vf->vf_id + hw->func_caps.vf_base_id;
reg = FIELD_PREP(VPINT_ALLOC_FIRST_M, device_based_first_msix) |
FIELD_PREP(VPINT_ALLOC_LAST_M, device_based_last_msix) |
VPINT_ALLOC_VALID_M;
wr32(hw, VPINT_ALLOC(vf->vf_id), reg);
Annotation
- Immediate include surface: `ice.h`, `ice_vf_lib_private.h`, `ice_base.h`, `ice_lib.h`, `ice_fltr.h`, `ice_dcb_lib.h`, `ice_flow.h`, `ice_eswitch.h`.
- Detected declarations: `function ice_free_vf_entries`, `function hash_for_each_safe`, `function ice_free_vf_res`, `function ice_dis_vf_mappings`, `function ice_free_vfs`, `function ice_for_each_vf`, `function ice_ena_vf_msix_mappings`, `function ice_ena_vf_q_mappings`, `function ice_ena_vf_mappings`, `function ice_calc_vf_reg_idx`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.