drivers/net/ethernet/intel/ice/ice_tspll.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/intel/ice/ice_tspll.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/intel/ice/ice_tspll.c- Extension
.c- Size
- 21758 bytes
- Lines
- 844
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
ice.hice_lib.hice_ptp_hw.h
Detected Declarations
function ice_tspll_default_freqfunction ice_tspll_check_paramsfunction ice_tspll_log_cfgfunction ice_tspll_cfg_e82xfunction ice_tspll_dis_sticky_bits_e82xfunction ice_tspll_cfg_e825cfunction ice_tspll_dis_sticky_bits_e825cfunction ice_tspll_cfg_pps_out_e825cfunction ice_tspll_cfgfunction ice_tspll_dis_sticky_bitsfunction ice_tspll_initfunction ice_tspll_bypass_mux_active_e825cfunction ice_tspll_cfg_bypass_mux_e825cfunction ice_tspll_get_div_e825cfunction ice_tspll_cfg_synce_ethdiv_e825c
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2025, Intel Corporation. */
#include "ice.h"
#include "ice_lib.h"
#include "ice_ptp_hw.h"
static const struct
ice_tspll_params_e82x e82x_tspll_params[NUM_ICE_TSPLL_FREQ] = {
[ICE_TSPLL_FREQ_25_000] = {
.refclk_pre_div = 1,
.post_pll_div = 6,
.feedback_div = 197,
.frac_n_div = 2621440,
},
[ICE_TSPLL_FREQ_122_880] = {
.refclk_pre_div = 5,
.post_pll_div = 7,
.feedback_div = 223,
.frac_n_div = 524288
},
[ICE_TSPLL_FREQ_125_000] = {
.refclk_pre_div = 5,
.post_pll_div = 7,
.feedback_div = 223,
.frac_n_div = 524288
},
[ICE_TSPLL_FREQ_153_600] = {
.refclk_pre_div = 5,
.post_pll_div = 6,
.feedback_div = 159,
.frac_n_div = 1572864
},
[ICE_TSPLL_FREQ_156_250] = {
.refclk_pre_div = 5,
.post_pll_div = 6,
.feedback_div = 159,
.frac_n_div = 1572864
},
[ICE_TSPLL_FREQ_245_760] = {
.refclk_pre_div = 10,
.post_pll_div = 7,
.feedback_div = 223,
.frac_n_div = 524288
},
};
/**
* ice_tspll_clk_freq_str - Convert time_ref_freq to string
* @clk_freq: Clock frequency
*
* Return: specified TIME_REF clock frequency converted to a string.
*/
static const char *ice_tspll_clk_freq_str(enum ice_tspll_freq clk_freq)
{
switch (clk_freq) {
case ICE_TSPLL_FREQ_25_000:
return "25 MHz";
case ICE_TSPLL_FREQ_122_880:
return "122.88 MHz";
case ICE_TSPLL_FREQ_125_000:
return "125 MHz";
case ICE_TSPLL_FREQ_153_600:
return "153.6 MHz";
case ICE_TSPLL_FREQ_156_250:
return "156.25 MHz";
case ICE_TSPLL_FREQ_245_760:
return "245.76 MHz";
default:
return "Unknown";
}
}
/**
* ice_tspll_default_freq - Return default frequency for a MAC type
* @mac_type: MAC type
*
* Return: default TSPLL frequency for a correct MAC type, -ERANGE otherwise.
*/
static enum ice_tspll_freq ice_tspll_default_freq(enum ice_mac_type mac_type)
{
switch (mac_type) {
case ICE_MAC_GENERIC:
return ICE_TSPLL_FREQ_25_000;
case ICE_MAC_GENERIC_3K_E825:
return ICE_TSPLL_FREQ_156_250;
default:
return -ERANGE;
}
}
Annotation
- Immediate include surface: `ice.h`, `ice_lib.h`, `ice_ptp_hw.h`.
- Detected declarations: `function ice_tspll_default_freq`, `function ice_tspll_check_params`, `function ice_tspll_log_cfg`, `function ice_tspll_cfg_e82x`, `function ice_tspll_dis_sticky_bits_e82x`, `function ice_tspll_cfg_e825c`, `function ice_tspll_dis_sticky_bits_e825c`, `function ice_tspll_cfg_pps_out_e825c`, `function ice_tspll_cfg`, `function ice_tspll_dis_sticky_bits`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.